Datasheet

LM5046

SNVS703G –FEBRUARY 2011–REVISED MARCH 2013

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Figure 17(a), SR1 and SR2 are turned-on simultaneously with a narrow pulse-width during the freewheeling

cycle. At the end of the freewheel cycle i.e. at the rising edge of the internal CLK, the SR FET in-phase with the

next power transfer cycle is kept on while the SR FET out of phase with it is turned-off. The in-phase SR FET is

kept on throughout the power transfer cycle and at the end of it, both the primary FETs and the in-phase SR

FETs are turned-off together. The synchronous rectifier outputs can be disabled by grounding the SSSR pin.

Figure 17. (a) Waveforms during Soft-Start (b) Waveforms after Soft-Start

Pre-Bias Startup

A common requirement for power converters is to have a monotonic output voltage start-up into a pre-biased

load i.e. a pre-charged output capacitor. In a pre-biased load condition, if the synchronous rectifiers are engaged

prematurely they will sink current from the pre-charged output capacitors resulting in an undesired output voltage

dip. This condition is undesirable and could potentially damage the power converter. The LM5046 utilizes unique

control circuitry to ensure intelligent turn-on of the synchronous rectifiers such that the output has a monotonic

startup. Initially, the SSSR capacitor is held at ground to disable the synchronous MOSFETs allowing the body

diode to conduct. The synchronous rectifier soft-start is initiated once it is established the duty cycle is controlled

by the COMP instead of the soft-start capacitor i.e. I

COMP

< 800µA and the voltage at the SS pin>2V. The SSSR

capacitor is then released and is charged by a 20µA current source. Further, as shown in Figure 18, a 1V offset

on the SSSR pin is used to provide additional delay. This delay ensures the output voltage is in regulation

avoiding any reverse current when the synchronous MOSFETs are engaged.

Soft-Stop

As shown in Figure 19, if the UVLO pin voltage falls below the 1.25V standby threshold, but above the 0.4V

shutdown threshold, the SSSR capacitor is soft-stopped with a 60µA current source (3 times the charging

current). Once the SSSR pin reaches the 1.0V threshold, both the SS and SSSR pins are immediately

discharged to GND. Soft-stopping the power converter gradually winds down the energy in the output capacitors

and results in a monotonic decay of the output voltage. During the hiccup mode, the same sequence is executed

except that the SSSR is discharged with a 120µA current source (6 times the charging current). In case of an

OVP, VCC UV, thermal limit or a VREF UV condition, the power converter hard-stops, whereby all of the control

outputs are driven to a low state immediately.

Product Folder Links: LM5046