Datasheet

RD(1,2) =
T
PA
, T
AP
3 pF
; For 20k < (1,2) < 100k
LM5046
www.ti.com SNVS703G –FEBRUARY 2011–REVISED MARCH 2013
(3)
If the desired dead-time for T
PA
is 60ns, then the RD1 will be 20 kΩ.
Figure 16. Synchronous Rectifier Timing Diagram
Soft-Start of the Synchronous Rectifiers
In addition to the basic soft-start already described, the LM5046 contains a second soft-start function that
gradually turns on the synchronous rectifiers to their steady-state duty cycle. This function keeps the
synchronous rectifiers off during the basic soft-start allowing a linear start-up of the output voltage even into pre-
biased loads. Then the SR output duty cycle is gradually increased to prevent output voltage disturbances due to
the difference in the voltage drop between the body diode and the channel resistance of the synchronous
MOSFETs. Initially, when bias is supplied to the LM5046, the SSSR capacitor is discharged by an internal
MOSFET. When the SS capacitor reaches a 2V threshold and once it is established that COMP is in control of
the duty cycle i.e. I
COMP
< 800µA, the SSSR discharge is released and SSSR capacitor begins charging with a
20µA current source. Once the SSSR cap crosses the internal 1V threshold, the LM5046 begins the soft-start of
the synchronous FETs. The SR soft-start follows a leading edge modulation technique, that is, the leading edge
of the SR pulse is soft-started as opposed trailing edge modulation of the primary FETs. As shown in
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