Datasheet

1
F
OSC
D
MAX
=
- (T
PA
)
( )
2
F
OSC
)(
LM5046
www.ti.com SNVS703G –FEBRUARY 2011–REVISED MARCH 2013
Gate Driver Outputs
The LM5046 provides four gate drivers: two floating high side gate drivers HO1 and HO2 and two ground
referenced low side gate drivers LO1 and LO2. Each internal driver is capable of sourcing 1.5A peak and sinking
2A peak. The low-side gate drivers are powered directly by the VCC regulator. The HO1 and HO2 gate drivers
are powered from a bootstrap capacitor connected between BST1/BST2 and HS1/HS2 respectively. An external
diode connected between VCC (anode pin) and BST (cathode pin) provides the high side gate driver power by
charging the bootstrap capacitor from VCC when the corresponding switch node (HS1/HS2 pin) is low. When the
high side MOSFET is turned on, BST1 rises to a peak voltage equal to VCC + V
HS1
where V
HS1
is the switch
node voltage.
The BST and VCC capacitors should be placed close to the pins of the LM5046 to minimize voltage transients
due to parasitic inductances since the peak current sourced to the MOSFET gates can exceed 1.5A. The
recommended value of the BST capacitor is 0.1μF or greater. A low ESR / ESL capacitor, such as a surface
mount ceramic, should be used to prevent voltage droop during the HO transitions.
Figure 15 illustrates the sequence of the LM5046 gate-drive outputs. Initially, the diagonal HO1 and LO2 are
turned-on together during the power transfer cycle, followed by the freewheel cycle, where HO1 and HO2 are
kept on. In the subsequent phase, the diagonal HO2 and LO1 are turned-on together during the power transfer
cycle, followed by a freewheel cycle, where LO1 and LO2 are kept on. The power transfer mode is often called
the active mode and the freewheel mode is often called as the passive mode. The dead-time between the
passive mode and the active mode, T
PA
, is set by the RD1 resistor and the dead-time between the active mode
and the passive mode, T
AP
, is set by the RD2 resistor. Refer to the APPLICATION INFORMATION section for
more details on the operation of the phase-shifted full-bridge topology.
If the COMP pin is open circuit, the outputs will operate at maximum duty cycle. The maximum duty cycle for
each phase is limited by the dead-time set by the RD1 resistor. If the RD1 resistor is set to zero then the
maximum duty cycle is slightly less than 50% due to the internally fixed dead-time. The internally fixed dead-time
is 30ns which does not vary with the operating frequency. The maximum duty cycle for each output can be
calculated from the following equation:
(2)
Where, T
PA
is the time set by the RD1 resistor and F
OSC
is the frequency of the oscillator. For example, if the
oscillator frequency is set at 400 kHz and the T
PA
time set by the RD1 resistor is 60ns, the resulting D
MAX
will be
equal to 0.488.
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