Datasheet

CS
R
FILTER
R
CS
LM5046
RAMP
CLK + LEB
CLK
Current
Sense
C
FILTER
SLOPE
100 PA
0
CS
R
FILTER
R
CS
LM5046
RAMP
CLK + LEB
CLK
Current
Sense
C
FILTER
SLOPE
100 PA
0
R
SLOPE
(a) (b)
LM5046
SNVS703G –FEBRUARY 2011–REVISED MARCH 2013 www.ti.com
Slope Pin
For duty cycles greater than 50% (25% for each phase), peak current mode control is subject to sub-harmonic
oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow duty
cycles. This can be eliminated by adding an artificial ramp, known as slope compensation, to the modulating
signal at the RAMP pin. The SLOPE pin provides a current source ramping from 0 to 100μA, at the frequency set
by the RT resistor, for slope compensation. The ramping current source at the SLOPE pin can be utilized in a
couple of different ways to add slope compensation to the RAMP signal:
1) As shown in Figure 14(a), the SLOPE and RAMP pins can be connected together through an appropriate
resistor to the CS pin. This configuration will inject current sense signal plus slope compensation to the RAMP
pin but CS pin will not see any slope compensation. Therefore, in this scheme slope compensation will not affect
the current limit.
2) In a second configuration, as shown in Figure 14(b), the SLOPE, RAMP and CS pins can be tied together. In
this configuration the ramping current source from the SLOPE pin will flow through the filter resistor and filter
capacitor, therefore both the CS pin and the RAMP pin will see the current sense signal plus the slope
compensation ramp. In this scheme, the current limit is compensated by the slope compensation and the current
limit onset point will vary.
If slope compensation is not required, for example in feed-forward voltage mode control, the SLOPE pin must be
connected to the AGND pin. When the RT pin is synched to an external clock, it is recommended to disable the
SLOPE pin and add slope compensation externally by connecting an appropriate resistor from the VCC pin to the
CS pin. Please refer to the APPLICATION INFORMATION section for more details.
(a) Slope Compensation Configured for PWM Only (No Current Limit Slope)
(b) Slope Compensation Configured for PWM and Current Limit
Figure 14. Slope Compensation Configuration
Soft-Start
The soft-start circuit allows the power converter to gradually reach a steady state operating point, thereby
reducing the start-up stresses and current surges. When bias is supplied to the LM5046, the SS capacitor is
discharged by an internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the
SS capacitor is released and is charged with a 20µA current source. Once the SS pin voltage crosses the 1V
offset, SS controls the duty cycle. The PWM comparator is a three input device; it compares the RAMP signal
against the lower of the signals between the soft-start and the loop error signal. In a typical isolated application,
as the secondary bias is established, the error amplifier on the secondary side soft-starts and establishes closed-
loop control, steering the control away from the SS pin.
One method to shutdown the regulator is to ground the SS pin. This forces the internal PWM control signal to
ground, reducing the output duty cycle quickly to zero. Releasing the SS pin begins a soft-start cycle and normal
operation resumes. A second shutdown method is presented in the UVLO section.
14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM5046