LM5046 www.ti.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Connection Diagram BST1 SR1 SLOPE COMP REF PGND HO2 SS HS2 SSSR RD1 LO2 RD2 SR2 BST2 RES VCC HO2 BST2 AGND HS2 RD2 PGND WQFN 28 SS OFF RD1 SR2 LO1 5 mm x 5 mm SSSR LO2 SR1 SS AGND COMP RES VCC BST1 RT TSSOP28 RT SLOPE REF LO1 HO1 CS HS1 HO1 VIN RAMP UVLO HS1 OVP OVP RAMP VIN CS UVLO SS OFF Figure 1. TSSOP28 Top View Figure 2.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 PIN DESCRIPTIONS (continued) TSSOP Pin WQFN Pin Name 7 3 REF 8 4 RT/SYNC 9 5 AGND 10 6 11 Description Application Information Output of a 5V reference Maximum output current is 15mA. Locally decouple with a 0.1µF capacitor. Oscillator Frequency Control and Frequency Synchronization The resistance connected between RT and AGND sets the oscillator frequency.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) VIN to GND HS to GND -0.3V to 105V (2) -5V to 105V BST1/BST2 to GND -0.3V to 116V BST1/BST2 to HS1/HS2 HO1/HO2 to HS1/HS2 -0.3V to 16V (3) -0.3V to BST1/BST2+0.3V (3) LO1/LO2/SR1/SR2 -0.3V to VCC+0.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 Electrical Characteristics Limits in standard typeface are for TJ = 25°C only; limits in boldface type apply the junction temperature range of -40°C to +125°C. Unless otherwise specified, the following conditions apply: VIN = 48V, RT = 25kΩ, RD1=RD2=20kΩ. No load on HO1, HO2, LO1, LO2, SR1, SR2, COMP=0V, UVLO=2.5V, OVP=0V, SSOFF=0V.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard typeface are for TJ = 25°C only; limits in boldface type apply the junction temperature range of -40°C to +125°C. Unless otherwise specified, the following conditions apply: VIN = 48V, RT = 25kΩ, RD1=RD2=20kΩ. No load on HO1, HO2, LO1, LO2, SR1, SR2, COMP=0V, UVLO=2.5V, OVP=0V, SSOFF=0V.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 Electrical Characteristics (continued) Limits in standard typeface are for TJ = 25°C only; limits in boldface type apply the junction temperature range of -40°C to +125°C. Unless otherwise specified, the following conditions apply: VIN = 48V, RT = 25kΩ, RD1=RD2=20kΩ. No load on HO1, HO2, LO1, LO2, SR1, SR2, COMP=0V, UVLO=2.5V, OVP=0V, SSOFF=0V.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Application Board Efficiency VCC vs ICC 100 36V EFFICIENCY (%) 90 48V 80 72V VOUT= 3.3V 70 60 50 5 10 15 20 25 LOAD CURRENT (A) 30 Figure 3. Figure 4. VVCC and VREF vs. VVIN IIN vs. VIN 6 5 VUVLO=3V IIN(V) 4 3 VUVLO=1V 2 1 VUVLO=0V 0 0 8 20 40 60 VIN(V) 80 Figure 5. Figure 6. VREF vs. IREF Oscillator Frequency vs. RT Figure 7. Figure 8.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Dead-Time TPA, TAP vs. Temperature Dead-Time TPA, TAP vs. RD1, RD2 Figure 9. Figure 10. CS Threshold vs. Temperature Figure 11.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM VOLTAGE REGULATOR VIN VCC 1.25V + OVP 0.4V - 20 éA 5V + HYSTERESIS VCC UVLO SHUTDOWN UVLO + - HO1 THERMAL LIMIT (160°C) STANDBY REF BST1 LOGIC 1.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The LM5046 PWM controller contains all of the features necessary to implement a Phase-Shifted Full-Bridge (PSFB) topology power converter using either current mode or voltage mode control. This device is intended to operate on the primary side of an isolated dc-dc converter with input voltage up to 100V.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Over Voltage Protection An external voltage divider can be used to set either an over voltage or an over temperature protection. During an OVP condition, the SS and SSSR capacitors are discharged and all the outputs are disabled. The divider must be designed such that the voltage at the OVP pin is greater than 1.25V when over voltage/temperature condition exists. Hysteresis is accomplished with an internal 20μA current source.
LM5046 www.ti.com • • • SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 voltage is ramped between 4.0V and 2.0V eight times. When the counter reaches eight, the RES pin voltage is pulled low and the soft-start capacitor is released to begin a soft-start sequence. The SS capacitor voltage slowly increases. When the SS voltage reaches 1.0V, the PWM comparator will produce the first narrow pulse.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Slope Pin For duty cycles greater than 50% (25% for each phase), peak current mode control is subject to sub-harmonic oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles. This can be eliminated by adding an artificial ramp, known as slope compensation, to the modulating signal at the RAMP pin.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 Gate Driver Outputs The LM5046 provides four gate drivers: two floating high side gate drivers HO1 and HO2 and two ground referenced low side gate drivers LO1 and LO2. Each internal driver is capable of sourcing 1.5A peak and sinking 2A peak. The low-side gate drivers are powered directly by the VCC regulator. The HO1 and HO2 gate drivers are powered from a bootstrap capacitor connected between BST1/BST2 and HS1/HS2 respectively.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Figure 15. Timing Diagram Illustrating the Sequence of Gate-Driver Outputs in the PSFB Topology Synchronous Rectifier Control Outputs (SR1 & SR2) Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low output voltage converters, compared to the diode rectification. The reduction of rectifier forward voltage drop (0.5V 1.
LM5046 www.ti.com RD(1,2) = SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 TPA, TAP 3 pF ; For 20k < (1,2) < 100k (3) If the desired dead-time for TPA is 60ns, then the RD1 will be 20 kΩ. Figure 16. Synchronous Rectifier Timing Diagram Soft-Start of the Synchronous Rectifiers In addition to the basic soft-start already described, the LM5046 contains a second soft-start function that gradually turns on the synchronous rectifiers to their steady-state duty cycle.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Figure 17(a), SR1 and SR2 are turned-on simultaneously with a narrow pulse-width during the freewheeling cycle. At the end of the freewheel cycle i.e. at the rising edge of the internal CLK, the SR FET in-phase with the next power transfer cycle is kept on while the SR FET out of phase with it is turned-off.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 2.0V SS 1.0V Primary Secondary Bias COMP 1.0V SSSR SR1, SR2 VOUT Prebiased Load Figure 18. Pre-Bias Voltage Startup Waveforms 1.25V VIN UVLO 1.25V 0.45V SS SSSR 1.0V Figure 19.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Soft-Stop Off The Soft-Start Off (SSOFF) pin gives additional flexibility by allowing the power converter to be configured for hard-stop during line UVLO and hiccup mode condition. If the SS OFF pin is pulled up to the 5V REF pin, the power converter hard-stops in any fault condition. Hard-stop drives each control output to a low state immediately. Refer to Table 2 for more details. Table 2.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 APPLICATION INFORMATION VIN VOUT HO1 VIN HO1 HO2 SW2 SW1 LMag SW2 SR2 LO2 IO + Imag LO1 LO2 Active to Passive Transition Power Transfer/Active Mode VOUT VIN HO1 HO2 SW1 SW2 LMag VIN HO1 LLeakage LMag SW1 SR1 LO1 HO2 LMag SW1 SR1 LO1 LLeak HO2 SW2 SR2 GND LO1 LO2 CParasitic LO2 Passive to Active Transition Freewheel/Passive Mode Figure 20.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Operating State 3 (Freewheel/Passive Mode) In the freewheel mode, unlike the conventional full-bridge topology where all the four primary FETs are off, in the PSFB topology the primary of the power transformer is shorted by activating either both the top FETs (HO1 and HO2) or both of the bottom FETs (LO1 and LO2) alternatively. In the current CLK cycle, the top FETs HO1 and HO2 are kept on together.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 phases results in flux imbalance that causes a dc buildup in the transformer. This continual dc buildup may eventually push the transformer into saturation. The volt-second asymmetry can be corrected by employing current mode control. In current mode control, a signal representative of the primary current is compared against an error signal to control the duty cycle.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com CURRENT MODE CONTROL USING THE LM5046 The LM5046 can be configured for current mode control by applying a signal proportional to the primary current to the RAMP pin. One way to achieve this is shown in Figure 23. The primary current can be sensed using a current transformer or sense resistor, the resulting signal is filtered and applied to the RAMP pin through a resistor used for slope compensation.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 VPWR 50 VIN LM5046 0.1 PF Figure 24. Input Transient Protection FOR APPLICATIONS WITH > 100V INPUT For applications where the system input voltage exceeds 100V, VIN can be powered from an external start-up regulator as shown in Figure 25. In this configuration, the VIN and VCC pins should be connected together. The voltage at the VCC and VIN pins must be greater than 10V (>Max VCC reference voltage) yet not exceed 16V.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Two external resistors can be used to program the maximum operational voltage for the power converter as shown in Figure 27. When the OVP pin voltage rises above the 1.25V threshold, an internal 20µA current source is enabled to raise the voltage at the OVP pin, thus providing threshold hysteresis. Resistance values for R1 and R2 can be determined from the following equations: R1 = R2 = VHYS 20 PA 1.25V x R1 VPWR -1.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 VPWR R1 UVLO 1.25V STANDBY LM5046 20 PA 0.4V R2 SHUTDOWN 5V 20 PA OVP STANDBY 1.25V R3 Figure 28. UVLO/OVP Divider Remote configuration of the controller’s operational modes can be accomplished with open drain device(s) connected to the UVLO pin as shown in Figure 29.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com LM5046 5V VPWR 20 PA NTC THERMISTOR T R1 OVP STANDBY 1.25V R2 Figure 30. Remote Thermal Protection CURRENT SENSE The CS pin receives an input signal representative of its transformer’s primary current, either from a current sense transformer or from a resistor located at the junction of source pin of the primary switches, as shown in Figure 31 and Figure 32, respectively.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 HICCUP MODE CURRENT LIMIT RESTART The operation of the hiccup mode restart circuit is explained in the FUNCTIONAL DESCRIPTION section. During a continuous current limit condition, the RES pin is charged with 30µA current source. The restart delay time required to reach the 1.0V threshold is given by: TCS = CRES x 1.0V 30 PA (10) This establishes the number of current limit events allowed before the IC initiates a hiccup restart sequence.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com AUGMENTING THE GATE DRIVE STRENGTH The LM5046 includes powerful 2A integrated gate drivers. However, in certain high power applications (>500W), it might be necessary to augment the strength of the internal gate driver to achieve higher efficiency and better thermal performance. In high power applications, typically, the I2xR loss in the primary MOSFETs is significantly higher than the switching loss.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 VIN LM5046 BST1 Q1 HO1 Q2 HS1 VCC LO1 PGND Figure 35. Bipolar Totem Pole Arrangement Alternatively, a low side gate driver such as LM5112 can be utilized instead of the discrete totem pole. The LM5112 comes in a small package with a 3A source and a 7A sink capability. While driving the high-side FET, the HS1 acts as a local ground and the boot capacitor between the BST and HS pins acts as VCC.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com PRINTED CIRCUIT BOARD LAYOUT The LM5046 current sense and PWM comparators are very fast and respond to short duration noise pulses. The components at the CS, COMP, SLOPE, RAMP, SS, SSSR, RES, UVLO, OVP, RD1, RD2, and RT pins should be physically close as possible to the IC, thereby minimizing noise pickup on the PC board trace inductance. Eliminating or minimizing via’s in these critical connections are essential.
LM5046 www.ti.com SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 APPLICATION CIRCUIT EXAMPLE The following schematic shows an example of a 100W phase-shifted full-bridge converter controlled by LM5046. The operating input voltage range is 36V to 75V, and the output voltage is 3.3V. The output current capability is 30 Amps. The converter is configured for current mode control with external slope compensation. An auxiliary winding is used to raise the VCC voltage to reduce the controller power dissipation.
LM5046 SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision F (March 2013) to Revision G • 34 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM5046MHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 LM5046SQ/NOPB WQFN RSG 28 1000 178.0 LM5046SQX/NOPB WQFN RSG 28 4500 330.0 6.8 10.2 1.6 8.0 16.0 Q1 12.4 5.3 5.3 1.3 8.0 12.0 Q1 12.4 5.3 5.3 1.3 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5046MHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM5046SQ/NOPB WQFN RSG 28 1000 210.0 185.0 35.0 LM5046SQX/NOPB WQFN RSG 28 4500 367.0 367.0 35.
MECHANICAL DATA PWP0028A MXA28A (Rev D) www.ti.
MECHANICAL DATA RSG0028A SQA28A (Rev B) www.ti.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
