Datasheet

LOGI
C
V
IN
V
CC
V
REF
SS
10PA
RT / SYNC
LOGIC
PGND
AGND
5V
REFERENCE
OSCILLATOR
DIVIDE BY 2
PUSH
CLK
CLK
V
CC
CS
TIME
OSC
45PA
LD
FB
0.5V
0.6V
PWM
5k
5V
1.4V
100k
50k
CLK + LEB
COMP
0.75V
SS
R
S
Q
Q
HD
UVLO
UVLO
HYSTERESIS
(20PA)
2.5V
2k
SS
0.45V
SHUTDOWN
COMPARATOR
ENABLE
ENABLE
V
CC
UVLO
9V SERIES
REGULATOR
+
-
+
-
+
-
+
-
DRIVE
R
PULL
DRIVE
R
+
-
SLOPE COMP
RAMP
GENERATOR
V
CC
OVERLAP
OR
DEAD TIME
CONTROL
+
-
LM5041
SNVS248D –AUGUST 2003–REVISED MARCH 2013 www.ti.com
Block Diagram
Figure 3. Simplified Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Product Folder Links: LM5041