Datasheet

LM5041B
www.ti.com SNVS605 –MAY 2009
PIN DESCRIPTIONS
Pin Pin
Pin # Pin Application Information
Name Description
1 V
IN
Source Input Voltage Input to start-up regulator. Input range 15V to 100V.
Inverting input for the internal error amplifier. The non-inverting input is connected to a
2 FB Feedback Signal
0.75V reference.
Output of the Internal There is an internal 5 kΩ resistor pull-up on this pin. The error amplifier provides an
3 COMP
Error Amplifier active sink.
Precision 5 volt Maximum output current: 10 mA. Locally decouple with a 0.1 µF capacitor. Reference
4 REF
reference output stays low until the V
CC
UV are satisfied.
Buck switch PWM control output. The maximum duty cycle clamp for this output
Main Buck PWM
5 HD corresponds to an off time of typically 240 ns per cycle. The LM5101 or LM5102 Buck
control output
stage gate driver can be used to level shift and drive the Buck switch MOSFET.
Buck Sync Switch Sync Switch control output. Inversion of HD output during normal operation. The LM5101
6 LD
control output or LM5102 lower drive can be used to drive the synchronous rectifier switch.
Output of the internal
high voltage start-up If an auxiliary winding raises the voltage on this pin above the regulation set-point, the
7 V
CC
regulator. Regulated to internal start-up regulator will shutdown, reducing the IC power dissipation.
9 volts.
Output of the push-pull
8 PUSH Output of the push-pull gate driver. Output capability of 1.5A peak .
drivers
Output of the push-pull
9 PULL Output of the push-pull gate driver. Output capability of 1.5A peak.
drivers
10 PGND Power ground Connect directly to analog ground.
11 AGND Analog ground Connect directly to power ground.
Current sense input to the PWM comparator (current mode control). There is a 50 ns
12 CS Current sense input leading edge blanking on this pin. If CS exceeds 0.5V, the PWM controller will go into
cycle by cycle current limit.
An external capacitor and an internal 10 µA current source, set the soft-start ramp. Both
13 SS Soft-Start control HD and LD will be forced to a low state if the SS pin is below the shutdown threshold of
0.45V.
An external resistor (R
SET
) sets the overlap time or dead time for the push-pull outputs.
Push-Pull overlap and
14 TIME A resistor connected between TIME and GND produces overlap. A resistor connected
dead time control
between TIME and REF produces dead time.
RT / Oscillator timing An external resistor sets the oscillator frequency. This pin will also accept an external
15
SYNC resistor pin and sync oscillator.
Line Under-Voltage An external divider from the power source sets the shutdown levels. Threshold of
16 UVLO
Shutdown operation equals 2.5V. Hysteresis is set by a switched internal current source (20 µA).
The exposed die attach pad of the WSON package should be connected to a PCB
WSON thermal pad at ground potential. For additional information on using TI's No Pull Back
SUB Die substrate
DAP WSON package, please refer to Application Note AN-1187 (literature number
SNOA401).
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