Datasheet

RT =
(1/F) - 235 x 10
-9
182 x 10
-12
:
LM5041B
SNVS605 –MAY 2009 www.ti.com
Current Limit/Current Sense
The LM5041B provides cycle-by-cycle over-current protection. If the voltage at the CS comparator (CS pin
voltage plus slope comp voltage) exceeds 0.5V the present buck stage duty cycle is terminated (cycle by cycle
current limit). A small RC filter located near the controller is recommended to filter current sense signals at the
CS pin. An internal MOSFET discharges the external CS pin for an additional 50 ns at the beginning of each
cycle to reduce the leading edge spike that occurs when the buck stage MOSFET is turned on.
The LM5041B current sense and PWM comparators are very fast, and may respond to short duration noise
pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated
with the CS filter must be placed close to the device and connected directly to the pins of the controller (CS and
GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the
sense resistor, which should also be located close to the IC. A resistor may be used for current sensing instead
of a transformer, located in the push-pull transistor sources, but a low inductance type of resistor is required.
When designing with a sense resistor, all of the noise sensitive low power grounds should be connected together
around the IC and a single connection should be made to the high current power ground (sense resistor ground
point).
Oscillator and Sync Capability
The LM5041B oscillator is set by a single external resistor connected between the RT pin and GND. To set a
desired oscillator frequency (F), the necessary RT resistor can be calculated from:
(1)
The buck stage will switch at the oscillator frequency and each push-pull output will switch at half the oscillator
frequency in a push-pull configuration. The LM5041B can also be synchronized to an external clock. The external
clock must have a higher frequency than the free running frequency set by the RT resistor. The clock signal
should be capacitively coupled into the RT pin with a 100 pF capacitor. A peak voltage level greater than 3V is
required for detection of the sync pulse. The sync pulse width should be set in the 15 ns to 150 ns range by the
external components. The RT resistor is always required, whether the oscillator is free running or externally
synchronized. The voltage at the RT pin is internally regulated to 2V. The RT resistor should be located very
close to the device and connected directly to the pins of the IC (RT and GND).
Slope Compensation
The PWM comparator compares the current sense signal to the voltage at the COMP pin. The output stage of
the internal error amplifier generally drives the COMP pin. At duty cycles greater than 50%, current mode control
circuits are subject to sub-harmonic oscillation. By adding an additional fixed ramp signal (slope compensation)
to the current sense ramp, oscillations can be avoided. The LM5041B integrates this slope compensation by
buffering the internal oscillator ramp and summing a current ramp generated by the oscillator internally with the
current sense signal. Additional slope compensation may be provided by increasing the source impedance of the
current sense signal.
Soft-Start and Shutdown
The soft-start feature allows the power converter to gradually reach the initial steady state operating point,
thereby reducing start-up stresses and surges. At power on, a 10 µA current is sourced out of the soft-start pin
(SS) to charge an external capacitor. The capacitor voltage will ramp up slowly and will limit the maximum duty
cycle of the buck stage. In the event of a fault as indicated by V
CC
Under-voltage, line Under-voltage the output
drivers are disabled and the soft-start capacitor is discharged to 0.7V. When the fault condition is no longer
present, a soft-start sequence will begin again and buck stage duty cycle will gradually increase as the soft-start
capacitor is charged.
The SS pin also serves as an enable input of HD and LD. Both HD and LD will be forced to a low state if the SS
pin is below the shutdown threshold of 0.45V.
12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Links: LM5041B