Datasheet

LM5035
www.ti.com SNVS428G –JANUARY 2006–REVISED MARCH 2013
PIN DESCRIPTIONS
HTSSOP WQFN
Name Description Application Information
PIN PIN
An external RC circuit from VIN sets the ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET.
1 23 RAMP Modulator ramp signal
Discharge is initiated by either the internal clock or the Volt •
Second clamp comparator.
An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO reaches the
0.4V threshold the VCC and REF regulators are enabled. When
2 24 UVLO Line Under-Voltage Lockout
UVLO reaches the 1.25V threshold, the SS pin is released and the
device enters the active mode. Hysteresis is set by an internal
current sink that pulls 23µA from the external resistor divider.
An external voltage divider from the power source sets the
shutdown levels. The threshold is 1.25V. Hysteresis is set by an
3 2 OVP Line Over-Voltage Protection
internal current source that sources 23µA into the external resistor
divider.
An external opto-coupler connected to the COMP pin sources
current into an internal NPN current mirror. The PWM duty cycle is
4 3 COMP Input to the Pulse Width Modulator maximum with zero input current, while 1mA reduces the duty cycle
to zero. The current mirror improves the frequency response by
reducing the AC voltage across the opto-coupler detector.
Normally biased at 2V. An external resistor connected between RT
Oscillator Frequency Control and and AGND sets the internal oscillator frequency. The internal
5 4 RT
Sync Clock Input. oscillator can be synchronized to an external clock with a frequency
higher than the free running frequency set by the RT resistor.
6 5 AGND Analog Ground Connect directly to Power Ground.
If CS exceeds 0.25V the output pulse will be terminated, entering
Current Sense input for current
7 6 CS cycle-by-cycle current limit. An internal switch holds CS low for 50ns
limit
after HO or LO switches high to blank leading edge transients.
An internal 55 µA current source charges an external capacitor to
set the soft-start rate. During a current limit restart sequence, the
8 7 SS Soft-start Input
internal current source is reduced to 1.2µA to increase the delay
before retry.
Timing programming pin for the LO An external resistor to ground sets the timing for the non-overlap
9 8 DLY
and HO to SR1 and SR2 outputs. time of HO to SR1 and LO to SR2.
If cycle-by-cycle current limit is exceeded during any cycle, a 22µA
current is sourced to the RES pin capacitor. If the RES capacitor
voltage reaches 2.5V, the soft-start capacitor will be fully discharged
10 9 RES Restart Timer
and then released with a pull-up current of 1.2µA. After the first
output pulse at LO (when SS > COMP offset, typically 1V), the SS
pin charging current will revert to 55µA.
An external diode is required from VCC to HB and an external
11 11 HB Boost voltage for the HO driver
capacitor is required from HS to HB to power the HO gate driver.
Connection common to the transformer and both power switches.
12 12 HS Switch node
Provides a return path for the HO gate driver.
Output of the high side PWM gate driver. Capable of sinking 2A
13 13 HO High side gate drive output.
peak current.
Output of the low side PWM gate driver. Capable of sinking 2A peak
14 14 LO Low side gate drive output.
current.
15 15 PGND Power Ground Connect directly to Analog Ground.
Output of the high voltage start-up If an auxiliary winding raises the voltage on this pin above the
16 16 VCC regulator. The VCC voltage is regulation setpoint, the Start-up Regulator will shutdown, thus
regulated to 7.6V. reducing the internal power dissipation.
Control output of the synchronous FET gate. Capable of 0.5A peak
17 17 SR2 Synchronous rectifier driver output.
current.
Control output of the synchronous FET gate. Capable of 0.5A peak
18 18 SR1 Synchronous rectifier driver output.
current.
Maximum output current is 20mA. Locally decoupled with a 0.1µF
19 19 REF Output of 5V Reference
capacitor.
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