Datasheet

LM5035
www.ti.com SNVS428G –JANUARY 2006–REVISED MARCH 2013
The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or
short circuit. This off time results in lower average input current and lower power dissipation within the power
components. It is recommended that the ratio of t2 / (t1 + t3) be in the range of 5 to 10 to take advantage of this
feature.
If the application requires no delay from the first detection of a current limit condition to the onset of the hiccup
mode (t1 = 0), the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup mode
entirely, the RES pin should be connected to ground (AGND).
Printed Circuit Board Layout
The LM5035 Current Sense and PWM comparators are very fast, and respond to short duration noise pulses.
The components at the CS, COMP, SS, OVP, UVLO, DLY and the RT pins should be as physically close as
possible to the IC, thereby minimizing noise pickup on the PC board tracks.
Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of
the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side
of the transformer should be connected via a dedicated PC board track to the AGND pin, rather than through the
ground plane.
If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistors
should be used. In this case, all the noise sensitive, low-current ground tracks should be connected in common
near the IC, and then a single connection made to the power ground (sense resistor ground point).
The gate drive outputs of the LM5035 should have short, direct paths to the power MOSFETs in order to
minimize inductance in the PC board traces. The SR control outputs should also have minimum routing distance
through the pulse transformers and through the secondary gate drivers to the sync FETs.
The two ground pins (AGND, PGND) must be connected together with a short, direct connection, to avoid jitter
due to relative ground bounce.
If the internal dissipation of the LM5035 produces high junction temperatures during normal operation, the use of
multiple vias under the IC to a ground plane can help conduct heat away from the IC. Judicious positioning of the
PC board within the end product, along with use of any available air flow (forced or natural convection) will help
reduce the junction temperatures. If using forced air cooling, avoid placing the LM5035 in the airflow shadow of
tall components, such as input capacitors.
Application Circuit Example
The following schematic shows an example of a 100W half-bridge power converter controlled by the LM5035.
The operating input voltage range (V
PWR
) is 36V to 75V, and the output voltage is 3.3V. The output current
capability is 30 Amps. Current sense transformer T2 provides information to the CS pin for current limit
protection. The error amplifier and reference, U3 and U5 respectively, provide voltage feedback via opto-coupler
U4. Synchronous rectifiers Q4, Q5, Q6 and Q7 minimize rectification losses in the secondary. An auxiliary
winding on transformer T1 provides power to the LM5035 VCC pin when the output is in regulation. The input
voltage UVLO thresholds are ≊34V for increasing V
PWR
, and ≊32V for decreasing V
PWR
. The circuit can be shut
down by driving the ON/OFF input (J2) below 1.25V with an open-collector or open-drain circuit. An external
synchronizing frequency can be applied through a 100pF capacitor to the RT input (U1 pin 5). The regulator
output is current limited at ≊34A.
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