Datasheet

R
2
=
1.25V x R
1
V
PWR
± 1.25V ± (23 PA x R
1
)
R
1
=
V
HYS
23 PA
LM5035
SNVS428G –JANUARY 2006–REVISED MARCH 2013 www.ti.com
PROGRAMMABLE DELAY (DLY)
The R
DLY
resistor programs the delays between the SR1 and SR2 signals and the HO and LO driver outputs.
Figure 15 shows the relationship between these outputs. The DLY pin is nominally set at 2.5V and the current is
sensed through R
DLY
to ground. This current is used to adjust the amount of deadtime before the HO and LO
pulse (T1) and after the HO and LO pulse (T2). Typically R
DLY
is in the range of 10kΩ to 100kΩ. The deadtime
periods can be calculated using the following formulae:
T1 = [R
DLY
x 2.8ps] + 20ns (7)
T2 = [R
DLY
x 1.35ps] + 6ns (8)
T1 and T2 can be set to minimum by not connecting a resistor to DLY, connecting a resistor greater than 300kΩ
from DLY to ground, or connecting DLY to the REF pin. This may cause lower than optimal system efficiency if
the delays through the SR signal transformer network, the secondary gate drivers and the SR MOSFETs are
greater than the delay to turn on the HO or LO MOSFETs. Should an SR MOSFET remain on while the opposing
primary MOSFET is supplying power through the power transformer, the secondary winding will experience a
momentary short circuit, causing a significant power loss to occur.
When choosing the R
DLY
value, worst case propagation delays and component tolerances should be considered
to assure that there is never a time where both SR MOSFETs are enabled AND one of the primary side
MOSFETs is enabled. The time period T1 should be set so that the SR MOSFET has turned off before the
primary MOSFET is enabled. Conversely, T1 and T2 should be kept as low as tolerances allow to optimize
efficiency. The SR body diode conducts during the time between the SR MOSFET turns off and the power
transformer begins supplying energy. Power losses increase when this happens since the body diode voltage
drop is many times higher than the MOSFET channel voltage drop. The interval of body diode conduction can be
observed with an oscilloscope as a negative 0.7V to 1.5V pulse at the SR MOSFET drain.
UVLO AND OVP VOLTAGE DIVIDER SELECTION FOR R1, R2, AND R3
Two dedicated comparators connected to the UVLO and OVP pins are used to detect under-voltage and over-
voltage conditions. The threshold value of these comparators, V
UVLO
and V
OVP
, is 1.25V (typical). The two
functions can be programmed independently with two voltage dividers from VIN to AGND as shown in Figure 20
and Figure 21, or with a three-resistor divider as shown in Figure 22. Independent UVLO and OVP pins provide
greater flexibility for the user to select the operational voltage range of the system. Hysteresis is accomplished by
23µA current sources (I
UVLO
and I
OVP
), which are switched on or off into the sense pin resistor dividers as the
comparators change state.
When the UVLO pin voltage is below 0.4V, the controller is in a low current shutdown mode. For a UVLO pin
voltage greater than 0.4V but less than 1.25V the controller is in standby mode. Once the UVLO pin voltage is
greater than 1.25V, the controller is fully enabled. Two external resistors can be used to program the minimum
operational voltage for the power converter as shown in Figure 20. When the UVLO pin voltage falls below the
1.25V threshold, an internal 23 µA current sink is enabled to lower the voltage at the UVLO pin, thus providing
threshold hysteresis. Resistance values for R1 and R2 can be determined from the following equations.
(9)
(10)
where V
PWR
is the desired turn-on voltage and V
HYS
is the desired UVLO hysteresis at V
PWR
.
For example, if the LM5035 is to be enabled when V
PWR
reaches 34V, and disabled when VPWR is decreased to
32V, R1 should be 87kΩ, and R2 should be 3.54kΩ. The voltage at the UVLO pin should not exceed 7V at any
time. Be sure to check both the power and voltage rating (0603 resistors can be rated as low as 50V) for the
selected R1 resistor.
20 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5035