Datasheet

LM5034
www.ti.com SNVS347A –FEBRUARY 2005–REVISED APRIL 2013
PIN DESCRIPTIONS
PIN NAME DESCRIPTION APPLICATIONS INFORMATION
1 OVLP Active Clamp Overlap Adjust An external resistor (10 kΩ to 100 kΩ) sets the overlap time of the active clamp
outputs relative to the main outputs for both Controller 1 and Controller 2. The
overlap time results in deadtime between each main switch and its active clamp
switch.
2 VIN Input Supply Input to the startup regulator. The operating input range is 13V to 100V with
transient capability to 105V.
3 COMP1 PWM Control, Controller 1 The COMP1 input provides voltage feedback to the PWM comparator inverting
input of Controller 1 through a 3:1 divider. The OUT1 duty cycle increases as
the COMP1 voltage increases. An internal 5KΩ pull-up resistor to +5.0V
provides bias current to an opto-coupler transistor.
4 CS1 Current Sense Input, Controller 1 Input for current mode control and the current limit sensing. If the CS1 pin
exceeds 0.5V the OUT1 pulse is terminated producing cycle-by-cycle current
limiting. External resistance connected to CS1 will adjust (increase) PWM slope
compensation. This pin's voltage must not exceed 1.25V.
5 SS1 Soft-start, Controller 1 An internal 50 µA current source charges an external capacitor to set the soft-
start rate. During a current limit restart sequence, the internal current source is
reduced to 1 µA to increase the delay before retry. Forcing SS1 below 0.5V
shuts off Controller 1.
6 UVLO VIN Under-Voltage Lockout An external resistor divider sets the input voltage threshold to enable the
LM5034. The UVLO comparator reference voltage is 1.25V. A switched 20 µA
current source provides adjustable UVLO hysteresis. The UVLO pin voltage
also controls the maximum duty cycle as described in the Functional
Description section.
7 VCC1 Start-up regulator output, Controller 1 Output of the 7.7V high voltage start-up regulator for Controller 1. The sum of
the currents drawn from VCC1 and VCC2 should not exceed 19 mA.
8 OUT1 Main Gate Driver, Controller 1 Gate driver output to the primary side switch for Controller 1. OUT1 swings
between VCC1 and GND1 at a frequency equal to half the oscillator frequency.
9 AC1 Active Clamp Driver, Controller 1 Gate driver output to the active clamp P-channel MOSFET for Controller 1. The
AC1 pulse overlaps the leading and trailing edges of the OUT1 pulse by an
interval set by the OVLP pin resistor. The overlap produces deadtime between
the main switch transistor and the P-channel active clamp transistor.
10 GND1 Ground, Controller 1 Ground connection for Controller 1 including gate drivers, PWM controller, soft-
start and support functions.
11 GND2 Ground, Controller 2 Ground connection for Controller 2 including gate drivers, PWM controller and
soft-start.
12 AC2 Active Clamp Driver, Controller 2 Gate driver output to the active clamp P-channel MOSFET for Controller 2. The
AC2 pulse overlaps the leading and trailing edges of the OUT2 pulse by an
interval set by the OVLP pin resistor. The overlap produces deadtime between
the main switch transistor and the P-channel active clamp transistor.
13 OUT2 Main Gate Driver, Controller 2 Gate driver output to the primary side switch for Controller 2. OUT2 swings
between VCC2 and GND2 at a frequency equal to half the oscillator frequency.
14 VCC2 Start-up regulator output, Controller 2 Output of the 7.7V high voltage start-up regulator for Controller 2. The sum of
the currents drawn from VCC1 and VCC2 should not exceed 19 mA.
15 RES Hiccup mode restart adjust An external capacitor sets the time delay before forced restart during a
sustained period of cycle-by-cycle current limiting. The hiccup mode
comparator threshold is 2.55V.
16 SS2 Soft-start, Controller 2 An internal 50 µA current source charges an external capacitor to set the soft-
start rate. During a current limit restart sequence, the internal current source is
reduced to 1µA to increase the delay before retry. Forcing SS2 below 0.5V
shuts off Controller 2.
17 CS2 Current Sense Input, Controller 2 Input for current mode control and the current limit sensing. If the CS2 pin
exceeds 0.5V the OUT2 pulse is terminated producing cycle-by-cycle current
limiting. External resistance connected to CS2 will adjust (increase) PWM slope
compensation. This pin's voltage must not exceed 1.25V.
18 COMP2 PWM Control, Controller 2 The COMP2 input provides voltage feedback to the PWM comparator inverting
input of Controller 2 through a 3:1 divider. The OUT2 duty cycle increases as
the COMP2 voltage increases. An internal 5kΩ pull-up resistor to +5.0V
provides bias current to the opto-coupler transistor.
19 DCL Duty Cycle Limit An external resistor sets the maximum allowed duty cycle at OUT1 and OUT2.
20 RT/SYNC Oscillator Adjust and Synchronizing An external resistor sets the oscillator frequency. This pin also accepts ac-
input coupled synchronization pulses from an external source.
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