Datasheet

UVLO
LM5034
1.25V
20 PA
Max. Duty
Cycle Limiter
R1A
R1B
R2
Z1
V
PWR
LM5034
SNVS347A –FEBRUARY 2005–REVISED APRIL 2013 www.ti.com
LINE VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE
As V
PWR
increases and the voltage at UVLO follows, the maximum allowed duty cycle decreases according to
the graph of Figure 13. Using values from the example above (R1 = 150 kΩ, R2 = 10 kΩ in Figure 29), the
maximum duty cycle varies as shown in Figure 14. If it is desired to increase the slope of the ramp in Figure 14,
Figure 35 shows a suggested configuration. After the LM5034 is enabled, Z1 clamps the voltage across R1B,
and UVLO increases with V
PWR
at a rate determined by the ratio R2/(R1A + R2).
Figure 35. Altering the Slope of Duty Cycle vs. V
PWR
USER DEFINED MAX DUTY CYCLE
The maximum allowed duty cycle at OUT1 and OUT2 can be set with a resistor from DCL to GND1. See
Figure 12 and Equation 2. The default maximum duty cycle (80%) determined by the internal clock signals can
be selected by setting R
DCL
= R
T
. The oscillator frequency setting resistor (R
T
) must be determined before R
DCL
is
selected. The DCL pin should not be left open.
PRINTED CIRCUIT (PC) BOARD LAYOUT
The LM5034 Current Sense and PWM comparators are very fast, and respond to short duration noise pulses.
The components at the CS, COMP, SS, DCL, UVLO, OVLP and the RT/SYNC pins should be as physically close
as possible to the IC, thereby minimizing noise pickup in the PC board tracks.
Layout considerations are critical for the current sense filter. If current sense transformers are used, both leads of
each transformer secondary should be routed to the sense filter components and to the IC pins. The ground side
of each transformer should be connected via a dedicated PC board track to its appropriate GND pin, rather than
through the ground plane.
If the current sense circuits employ sense resistors in the drive transistor sources, low inductance resistors
should be used. In this case, all the noise sensitive low current ground tracks should be connected in common
near the IC, and then a single connection made to the power ground (sense resistor ground point). The outputs
of the LM5034 should have short direct paths to the power MOSFETs in order to minimize inductance in the PC
board traces.
The two ground pins (GND1, GND2) must be connected together with a short direct connection to avoid jitter due
to relative ground bounce in the operation of the two regulators.
If the internal dissipation of the LM5034 produces high junction temperatures during normal operation, the use of
wide PC board traces can help conduct heat away from the IC. Judicious positioning of the PC board within the
end product, along with use of any available air flow (forced or natural convection) can help reduce the junction
temperatures.
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