Datasheet

t
VCC
=
(C1 + C2) x 7.6V
I
CC(Lim)
UVLO
LM5034
1.25V
20 PA
Max. Duty
Cycle Limiter
R1
R2
V
PWR
Shutdown
Control
UVLO
LM5034
1.25V
20 PA
Max. Duty
Cycle Limiter
R1
R2
V
PWR
Enable V
CC
Regulator
and Output Drivers
R2 =
1.25 x R1
V
PWR
- 1.25
LM5034
SNVS347A –FEBRUARY 2005–REVISED APRIL 2013 www.ti.com
UVLO
The under-voltage lockout threshold (UVLO) is internally set at 1.25V at the UVLO pin. With two external
resistors as shown in Figure 29, the LM5034 is enabled when V
PWR
exceeds the programmed threshold voltage.
When V
PWR
is above the threshold, the internal 20 µA current source is enabled to raise the voltage at the UVLO
pin, providing hysteresis. R1 and R2 are determined from the following equations:
R1 = V
HYS
/20 µA (4)
(5)
where V
HYS
is the desired UVLO hysteresis at V
PWR
, and V
PWR
in the second equation is the turn-on voltage. For
example, if the LM5034 is to be enabled when V
PWR
reaches 20V, and disabled when V
PWR
is decreased to 17V,
R1 calculates to 150 kΩ, and R2 calculates to 10 kΩ. The voltage at UVLO should not exceed 6V at any time.
Figure 29. UVLO Circuit
The LM5034 can be remotely shutdown by taking the UVLO pin below 1.25V with an external open collector or
open drain device, as shown in Figure 30. The outputs, and the V
CC
regulator, are disabled, and the LM5034
enters a low power mode. To shut down one regulator without affecting the other, see Soft-Start.
Figure 30. Shutdown Control
VCC1, VCC2
The capacitors at each VCC pin provide not only regulator noise filtering and stability, but also prevents VCC
from dropping to the lower under-voltage threshold level (UVT = 6.2V) when the output drivers source current
surges to the external MOSFET gates. Additionally, the capacitors provide a necessary time delay during startup.
The time delay allows the internal circuitry of the LM5034 and associated external circuitry to stabilize before V
CC
reaches the upper UVT threshold level (7.6V), at which time the outputs are enabled and the soft-start sequence
begins. V
CC
is nominally regulated at 7.7V. The delay to the UVT level (Figure 5) is calculated from the following:
(6)
where C1 and C2 are the capacitors at VCC1 and VCC2, and I
CC(Lim)
is the V
CC
regulator’s current limit. If the
capacitors are 0.1 µF each, the nominal I
CC(Lim)
of 22 mA provides a delay of approximately 69 µs. The V
CC
capacitor values should range between 0.1 µF and 25 µF, and they should be the same value. Experimentation
with the final design may be necessary to determine the optimum value for the V
CC
capacitors.
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