Datasheet

LM5034
www.ti.com SNVS347A –FEBRUARY 2005–REVISED APRIL 2013
Cycle-by-Cycle Current Limit
Each CS pin is designed to accept a signal representative of its transformer primary current. If the voltage at CS
exceeds 0.5V the current sense comparator terminates the present main output driver (OUT pin) pulse. If the
high current fault persists, the controller operates with constant peak switch current in a cycle-by-cycle current
limit mode, and a Hiccup Mode Current Limit Restart cycle begins (see below).
Each CS pin is internally connect to ground through a 30Ω resistor during the main output off time to discharge
external filter capacitance. The discharge device remains on for an additional 50 ns after the main output driver
switches high to blank leading edge transients in the current sensing circuit. Discharging the CS pin filter each
cycle and blanking leading edge spikes reduces the filter requirement which improves the current sense
response time.
The current sense comparators are fast and respond to short duration noise pulses. The external circuitry at
each CS pin should include an R-C filter to suppress noise. Layout considerations are critical for the current
sense filter and the sense resistor. See Applications Information for PC board layout guidelines.
Hiccup Mode Current Limit Restart
If cycle-by-cycle current limiting continues in either or both controllers for a sufficient period of time, the Current
Limit Restart circuit disables both regulators and initiates a soft-start sequence after a programmable delay. The
duration of cycle-by-cycle current limiting before turn-off occurs is programmed by the value of the external
capacitor at the RES pin. The dwell time before output switching resumes is programmed by the value of the
Soft-start capacitor(s). The circuit is detailed in Figure 22 and the timing is shown in Figure 23. A description of
this circuit’s operation is as follows:
a) No current limit detected:
The 10 µA discharge current source at RES is enabled pulling the RES pin to ground.
b) Current limit repeatedly detected at both CS inputs:
The 20 µA current source at RES is enabled continuously to charge the RES pin capacitor as shown in
Figure 23. The current limit comparators also terminate the PWM output pulses to provide a cycle-by-cycle
current limiting. When the voltage on the RES capacitor reaches the 2.55V restart comparator threshold, the
comparator sets the Restart Latch which produces the following restart sequence:
• The SS1 and SS2 pin charging currents are reduced from 50µA to 1 µA,
• An internal MOSFET is turned on to discharge the RES pin capacitor.
• The internal MOSFETs at SS1 and SS2 are turned on to discharge the Soft-start capacitors.
• COMP1 and COMP2 follow SS1 and SS2 respectively and reduce the PWM duty cycles to zero
• When the voltages at the SS pins fall below 200mV, the internal MOSFETs at the SS pins are turned off
allowing the SS pins to be charged by the 1µA current sources.
• When either SS pin reaches ≊1.5V its PWM controller produces the first pulse of a soft-start sequence which
resets the Restart Latch. The SS charging currents are increased to 50 µA and the soft-start sequence
continues at the normal rate.
If the overload condition still exists, the voltage at RES begins to increase again and repeat the restart cycle as
shown in Figure 23. If the overload condition has been cleared, the RES pin is held at ground by the 10 µA
current source.
c) Current limit repeatedly detected at one of the two CS inputs:
In this condition the RES pin capacitor is charged by the 20 µA current source once each clock cycle of the
current limited regulator (CLK1 or CLK2), and discharged by the 10 µA current source once each clock cycle of
the unaffected regulator. The voltage at the RES pin increases one fourth as fast as in case b) described above.
The current limited regulator operates in a cycle-by-cycle current limit mode until the voltage at RES reaches the
2.55V threshold. When the Restart Comparator output switches high the Restart Latch is set, both SS pin
capacitors are discharged to disable the regulator channels, and a restart sequence begins as described in case
b) above.
To determine the value of the RES pin capacitor, see Applications Information.
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