Datasheet

Load
Power
Transformer
LM5034
5.0V
PWM
Comparator
COMP1
Slope Comp.
2k
42k
5k
Error
Amplifier
Current
Sense
5k
10k
CS1
RCS
RF
CF
LEB
30
V
PWR
45 PA
V
REF
V
OUT
|
R
T
=
17100
F
S
- 0.001(F
S
- 400)
LM5034
SNVS347A –FEBRUARY 2005–REVISED APRIL 2013 www.ti.com
Oscillator
The oscillator frequency is set with an external resistor R
T
connected between the RT/SYNC and GND1 pins.
The resistor value is calculated from:
(1)
where F
S
is the desired oscillator frequency in kHz (maximum of 2 MHz), and R
T
is in kΩ. See Figure 11. The
two gate driver outputs (OUT1 and OUT2) switch at half the oscillator frequency and 180° out of phase with each
other. The voltage at the R
T
/SYNC pin is internally regulated at 2.0V. The R
T
resistor should be located as close
as possible to the LM5034 with short direct connections to the pins.
The LM5034 can be synchronized to an external clock by applying a narrow clock pulse to the R
T
/SYNC pin. See
Applications Information for details on this procedure. The R
T
resistor is always required, whether the oscillator is
free running or externally synchronized.
PWM Comparator/Slope Compensation
The PWM comparator of each controller compares a slope compensated current ramp signal with the loop error
voltage derived from the COMP pin. The COMP voltage is typically controlled by an external error
amplifier/optocoupler feedback circuit to regulate the converter output voltage. Internally, the voltage at the
COMP pin passes through two level shifting diodes and a gain reducing 3:1 resistor divider (see Figure 21). The
compensated current ramp signal is a combination of the current waveform at the CS pin, and an internally
generated ramp derived from the internal clock. At duty cycles greater than 50% current mode control circuits are
prone to subharmonic oscillation. By adding a small fixed ramp to the external current sense signal oscillations
can be avoided. The internal ramp has an amplitude of 45 µA and is sourced into an internal 2kΩ resistor, and a
42 kΩ resistor in parallel with the external impedance at the CS pin. The ramp current also flows through the
external impedance connected to the CS pin and thus, the amount of slope compensation can be adjusted by
varying the external circuit at the CS pin.
The output of the PWM comparator provides the pulse width information to the output drivers. This comparator is
optimized for speed in order to achieve minimum controllable duty cycles. The comparator’s output duty cycle is
0% for V
COMP
≤1.5V, and increases as V
COMP
increases.
If either Soft-start pin is pulled low (internally or externally) the corresponding COMP pin is pulled down with it,
forcing the output duty cycle to zero. When the Soft-start pin voltage increases, the COMP pin is allowed to
increase. An internal 5 kΩ resistor connected from COMP to an internal 5.0V supply provides a pull-up for the
COMP pin and bias current to the collector of the opto-coupler transistor.
Figure 21. Typical Feedback Network
14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5034