Datasheet

190
192
194
196
198
200
202
204
206
208
210
FREQUENCY @ OUT1, OUT2 (kHz)
-50 0 50 100 150
R
T
= 42.2k
TEMPERATURE (
o
C)
-50 0 50 100 150
TEMPERATURE (
o
C)
OVERLAP TIME (ns)
85
90
95
100
105
110
115
R
OVLP
= 70k
0 20 40 60 80
0
20
40
60
80
100
MAXIMUM DUTY CYCLE (%)
VOLTAGE AT VIN (V)
R
1
= 150 k:
R
2
= 10 k:
Figure 27
0 20 40 60 80 100
0
30
60
90
120
150
OVERLAP TIME (ns)
R
OVLP
(k:)
0 0.2 0.4 0.6 0.8 1.0
0
20
40
60
80
100
MAXIMUM DUTY CYCLE (%)
R
DCL
/R
T
UVLO Pin = 1.26V
0 1.0 2.0 3.0 4.0 5.0
0
20
40
60
80
100
MAXIMUM DUTY CYCLE (%)
VOLTAGE AT UVLO PIN (V)
1.25V
LM5034
www.ti.com SNVS347A –FEBRUARY 2005–REVISED APRIL 2013
Typical Performance Characteristics (continued)
User Defined Maximum Duty Cycle vs. R
DCL
Resistor Maximum Duty Cycle vs. UVLO Voltage
Figure 12. Figure 13.
Maximum Duty Cycle vs. VIN (Figure 31) Active Clamp Overlap Time vs. R
OVLP
Figure 14. Figure 15.
Frequency vs. Temperature Overlap Time vs. Temperature
Figure 16. Figure 17.
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