Datasheet

UVLO
LM5032
1.25V
20 PA
Max. Duty
Cycle Limiter
R1A
R1B
R2
Z1
V
PWR
C
SS1
PWM
Controller #1
Softstart
#1
COMP1
SS1
Shutdown
Control
PWM
Controller #2
COMP2
To Output
Drivers
Softstart
# 2
C
SS2
SS2
Coupler
Opto-
Coupler
Opto-
LM5032
LM5032
www.ti.com SNVS344A –MARCH 2005–REVISED APRIL 2013
With a 0.1 µF capacitor at SS, t2 is ≊150 ms.
Experimentation with the startup sequence and over-current restart condition is usually necessary to determine
the appropriate value for the SS capacitors.
To shutdown one regulator without affecting the other, ground the appropriate SS pin with an open collector or
open drain device as shown in Figure 30. The SS pin forces the COMP pin to ground which reduces the PWM
duty cycle to zero for that regulator. Releasing the SS pin allows normal operation to resume.
When the LM5032’s two controller channels are configured to provide a single high current output, SS1 and SS2
are typically connected together, requiring a single capacitor for the two pins.
Figure 30. Shutting Down One Regulator Channel
LINE VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE
As V
PWR
increases and the voltage at UVLO follows, the maximum allowed duty cycle decreases according to
the graph of Figure 12. Using values from the example above (R1 = 150 kΩ, R2 = 10 kΩ in Figure 25), the
maximum duty cycle varies as shown in Figure 13. If it is desired to increase the slope of the ramp in Figure 13,
Figure 31 shows a suggested configuration. After the LM5032 is enabled, Z1 clamps the voltage across R1B,
and UVLO increases with V
PWR
at a rate determined by the ratio R2/(R1A + R2).
Figure 31. Altering the Slope of Duty Cycle vs. V
PWR
USER DEFINED MAX DUTY CYCLE
The maximum allowed duty cycle at OUT1 and OUT2 can be set with a resistor from DCL to GND1. See
Figure 11 and Equation 2. The default maximum duty cycle (80%) determined by the internal clock signals can
be selected by setting R
DCL
= R
T
. The oscillator frequency setting resistor (R
T
) must be determined before R
DCL
is
selected. The DCL pin should not be left open.
PRINTED CIRCUIT (PC) BOARD LAYOUT
The LM5032 Current Sense and PWM comparators are very fast, and respond to short duration noise pulses.
The components at the CS, COMP, SS, DCL, UVLO, and the RT/SYNC pins should be as physically close as
possible to the IC, thereby minimizing noise pickup in the PC board tracks.
Layout considerations are critical for the current sense filter. If current sense transformers are used, both leads of
each transformer secondary should be routed to the sense filter components and to the IC pins. The ground side
of each transformer should be connected via a dedicated PC board track to its appropriate GND pin, rather than
through the ground plane.
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