Datasheet

LM5032
www.ti.com SNVS344A –MARCH 2005–REVISED APRIL 2013
Soft-start
Each soft-start circuit allows the corresponding regulator to gradually reach a steady state operating point,
thereby reducing startup current surges and output overshoot. Upon turn-on, both SS pins are internally held at
ground. When VCC increases past its under-voltage threshold (UVT), the SS pins are released and internal 50
µA current sources charge the external capacitors. The voltage at each COMP pin follows the SS pin, and when
COMP reaches ≊1.5V, the output pulses commence at a low duty cycle. The voltage at the SS pins continues to
increase and saturates at ≊5.0V, The voltage at each COMP pin increases to the value required for regulation
where it is controlled by its voltage feedback loop (see Figure 4).
If the internal Drivers Off line is activated (see Drivers Off, V
CC
Disable), both SS pins are internally grounded.
The SS pins pull the COMP pins to ground while the Driver Off signal disables the output drivers. When the
event which activated the Drivers Off line is cleared and Vcc exceeds its under-voltage threshold, the SS pins
are released. The internal 50 µA current sources then charge the external soft-start capacitors allowing each
regulator’s output duty cycle to increase.
If the Current Limit Restart threshold is reached due to repeated over-current detections, both SS pins (and the
COMP pins) are pulled to ground. The output drivers are disabled, and the 50 µA SS pin current sources are
reduced to 1 µA. After a short propagation delay the SS pins and the COMP pins are released, and the external
capacitors are charged up at a slow rate. When the COMP voltage reaches ≊ 1.5V, the output drivers are
enabled, and the current sources at the SS pins are increased to 50 µA. The output duty cycle then increases to
the value required for regulation.
To shutdown one regulator without affecting the other, ground the appropriate SS pin. This forces the COMP pin
to ground, reducing the output duty cycle to zero for that regulator. Releasing the SS pin allows normal operation
to resume.
Output Duty Cycle
The output driver’s duty cycle for each controller is normally controlled by comparing the voltage provided to the
COMP input by the external voltage feedback circuit with the current information at the CS pin. However, the
maximum duty cycle during transient or fault conditions may be intentionally limited by two other circuits, both of
which are common to the two controller channels.
User Defined Maximum Duty Cycle. The maximum allowed duty cycle can be set with the R
DCL
resistor
connected from the DCL pin to GND1, according to the following equation:
Maximum User Duty Cycle = 80% x R
DCL
/R
T
(2)
R
T
is the oscillator frequency programming resistor connected to the R
T
/SYNC pin. The value of the R
DCL
resistor
must be calculated after the R
T
resistor is selected. See Figure 11. Referring to the block diagram of Figure 3 the
voltage at the DCL pin is compared to the Ramp1 and Ramp2 signals, creating the UserMaxDC1 and
UserMaxDC2 timing signals. These signal are provided to the two 4-input AND gates to limit the PWM duty cycle
of both channels.
Line Voltage Maximum Duty Cycle. The voltage at the UVLO pin, normally proportional to the voltage at V
PWR
,
further limits the maximum duty cycle at high input voltages. Referring to Figure 13, when the UVLO pin is below
1.25V, the outputs are disabled. At UVLO = 1.25V the maximum allowed duty cycle is 80% (or less if limited by
the DCL resistor). As the UVLO pin voltage increases with V
PWR
, the maximum duty cycle decreases, reaching a
minimum of 10% at ≊4.5V. Referring to Figure 3 the UVLO voltage, after passing through an inverting gain stage,
is compared to the Ramp1 and Ramp2 signals generated by the oscillator. The output of these comparators are
the MaxDC1 and MaxDC2 timing signals. These signals are provided to the two 4-input AND gates which limit
the PWM pulses delivered to the output drivers.
Resulting Output Duty Cycle. The controller duty cycle is determined by the four signals into the 4-input AND
gates in Figure 3 (UserMaxDC, MaxDC, PWM and CLK). The output driver pulsewidth is equal to the least of
these four pulses. Whichever input of the AND gate transitions high-to-low first terminates the output driver’s on-
time.
Driver Outputs
OUT1, the primary switch driver for Controller 1 is designed to drive the gate of an N-channel MOSFET with 1.5A
sourcing current and 2.5A sinking current. The peak output levels are VCC and GND1. The ground return path
for Controller 1 is GND1. The corresponding pins for Controller 2 are OUT2 and GND2.
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5032