Datasheet

RES
SS1
and
SS2
OUT1
0V
2.55V
5.0V
t1 t2 t3
Current Limit Detected at
CS1 and/or CS2
OUT2
5
0
PA
1
PA
#1.5V
DC1
0.5V
Clk1, Clk2
0.5V
5.0V
2.55V
Restart
Comparator
Q
S
R
Drivers Off
Restart
Latch
DC2
SS1
SS2
To Output
Drivers
PWM #1
PWM #2
COMP2
COMP1
CS2
CS1
Current
Sense Circuit
RES
Soft-start #1
Soft-start #2
Voltage
Feedback
Voltage
Feedback
LM5032
SS2
SS1
49 PA
Restart
Current
Source
Logic
Drivers Off
SS1
200 mV
SS
Logic
SS2
200 mV
SS
Logic
Current
Limit
Current
Sense Circuit
20 PA
C
SS1
C
SS2
Current
Limit
49PA1PA
1PA
C
RES
10 PA
LM5032
SNVS344A –MARCH 2005–REVISED APRIL 2013 www.ti.com
continues at the normal rate.
If the overload condition still exists, the voltage at RES begins to increase again and repeat the restart cycle as
shown in Figure 20. If the overload condition has been cleared, the RES pin is held at ground by the 10 µA
current source.
c) Current limit repeatedly detected at one of the two CS inputs:
In this condition the RES pin capacitor is charged by the 20 µA current source once each clock cycle of the
current limited regulator, and discharged by the 10 µA current source once each clock cycle of the unaffected
regulator. The voltage at the RES pin increases one fourth as fast as in case b) described above. The current
limited regulator operates in a cycle-by-cycle current limit mode until the voltage at RES reaches the 2.55V
threshold. When the Restart Comparator output switches high the Restart Latch is set, both SS pin capacitors
are discharged to disable the regulator channels, and a restart sequence begins as described in case b) above.
To determine the value of the RES pin capacitor, see the Applications Information section.
Figure 19. Current Limit Restart Circuit
Figure 20. Current Limit Restart Timing
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