Datasheet

Load
Power
Transformer
LM5032
5.0V
PWM
Comparator
COMP1
Slope Comp.
2k
42k
5k
Error
Amplifier
Current
Sense
5k
10k
CS1
RCS
RF
CF
LEB
30
V
PWR
45 PA
V
REF
V
OUT
|
LM5032
www.ti.com SNVS344A –MARCH 2005–REVISED APRIL 2013
Figure 18. Typical Feedback Network
Cycle-by-Cycle Current Limit
Each CS pin is designed to accept a signal representative of its transformer primary current. If the voltage at CS
exceeds 0.5V the current sense comparator terminates the present main output driver (OUT pin) pulse. If the
high current fault persists, the controller operates with constant peak switch current in a cycle-by-cycle current
limit mode, and a Hiccup Mode Current Limit Restart cycle begins (see below).
Each CS pin is internally connect to ground through a 30Ω resistor during the main output off time to discharge
external filter capacitance. The discharge device remains on for an additional 50 ns after the main output driver
switches high to blank leading edge transients in the current sensing circuit. Discharging the CS pin filter each
cycle and blanking leading edge spikes reduces the filter requirement which improves the current sense
response time.
The current sense comparators are fast and respond to short duration noise pulses. The external circuitry at
each CS pin should include an R-C filter to suppress noise. Layout considerations are critical for the current
sense filter and the sense resistor. Refer to the Applications Information section for PC board layout guidelines.
Hiccup Mode Current Limit Restart
If cycle-by-cycle current limiting continues in either or both controllers for a sufficient period of time, the Current
Limit Restart circuit disables both regulators and initiates a soft-start sequence after a programmable delay. The
duration of cycle-by-cycle current limiting before turn-off occurs is programmed by the value of the external
capacitor at the RES pin. The dwell time before output switching resumes is programmed by the value of the
Soft-start capacitor(s). The circuit is detailed in Figure 19 and the timing is shown in Figure 20. A description of
this circuit’s operation is as follows:
a) No current limit detected:
The 10 µA discharge current source at RES is enabled pulling the RES pin to ground.
b) Current limit repeatedly detected at both CS inputs:
The 20 µA current source at RES is enabled continuously to charge the RES pin capacitor as shown in
Figure 20. The current limit comparators also terminate the PWM output pulses to provide a cycle-by-cycle
current limiting. When the voltage on the RES capacitor reaches the 2.55V restart comparator threshold, the
comparator sets the Restart Latch which produces the following restart sequence:
• The SS1 and SS2 pin charging currents are reduced from 50µA to 1 µA.
• An internal MOSFET is turned on to discharge the RES pin capacitor.
• The internal MOSFETs at SS1 and SS2 are turned on to discharge the Soft-start capacitors.
• COMP1 and COMP2 follow SS1 and SS2 respectively and reduce the PWM duty cycles to zero.
• When the voltages at the SS pins fall below 200mV, the internal MOSFETs at the SS pins are turned off
allowing the SS pins to be charged by the 1µA current sources.
• When either SS pin reaches ≊1.5V its PWM controller produces the first pulse of a soft-start sequence which
resets the Restart Latch. The SS charging currents are increased to 50 µA and the soft-start sequence
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