Datasheet

R
T
=
17100
F
S
- 0.001(F
S
- 400)
LM5032
SNVS344A –MARCH 2005–REVISED APRIL 2013 www.ti.com
When enabled, the V
CC
regulated output is 7.7V ±4% with current limited to a minimum of 19 mA (typically 22
mA). The regulator’s output impedance is ≊ 6Ω.
The VCC pin requires a capacitor to ground for stability, as well as to provide the surge currents to the external
MOSFETs via the gate driver outputs. The capacitor should be physically close to the VCC and GND pins.
In most applications it is necessary to power V
CC
from an external source as the average current required at the
output drivers may exceed the current capability of the internal regulator and/or the thermal capability of the
LM5032 package (see Figure 7). Normally the external source is derived from the converter’s power stage once
the LM5032 outputs are active. Refer to the Applications Information section for more information.
Drivers Off, V
CC
Disable
Referring to Figure 17, Drivers Off and V
CC
Disable are internal signals which, when active disable portions of the
LM5032. If the UVLO pin is below 1.25V, or if the thermal shutdown activates, the V
CC
Disable line switches high
to disable the V
CC
regulator. UVLO also activates the Drivers Off signal to disable the output drivers, connect the
SS1, SS2, COMP1, COMP2 and RES pins to ground, and enable the 50 µA Soft-start current sources.
If the V
CC
voltage falls below the under-voltage threshold of 6.2V , the UVT comparator activates only the Drivers
Off signal. The output drivers are disabled but the V
CC
regulator is not disabled. Additionally, the CS1, CS2, SS1,
SS2, COMP1, COMP2 and RES pins are internally grounded, and the 50 µA Soft-start current sources are
enabled.
Oscillator
The oscillator frequency is set with an external resistor R
T
connected between the RT/SYNC and GND1 pins.
The resistor value is calculated from:
(1)
where F
S
is the desired oscillator frequency in kHz (maximum of 2 MHz), and R
T
is in kΩ. See Figure 10. The
two gate driver outputs (OUT1 and OUT2) switch at half the oscillator frequency and 180° out of phase with each
other. The voltage at the R
T
/SYNC pin is internally regulated at 2.0V. The R
T
resistor should be located as close
as possible to the LM5032 with short direct connections to the pins.
The LM5032 can be synchronized to an external clock by applying a narrow clock pulse to the R
T
/SYNC pin. See
the Applications Information section for details on this procedure. The R
T
resistor is always required, whether the
oscillator is free running or externally synchronized.
PWM Comparator/Slope Compensation
The PWM comparator of each controller compares a slope compensated current ramp signal with the loop error
voltage derived from the COMP pin. The COMP voltage is typically controlled by an external error
amplifier/optocoupler feedback circuit to regulate the converter output voltage. Internally, the voltage at the
COMP pin passes through two level shifting diodes and a gain reducing 3:1 resistor divider (see Figure 18). The
compensated current ramp signal is a combination of the current waveform at the CS pin, and an internally
generated ramp derived from the internal clock. At duty cycles greater than 50% current mode control circuits are
prone to subharmonic oscillation. By adding a small fixed ramp to the external current sense signal oscillations
can be avoided. The internal ramp has an amplitude of 45 µA and is sourced into an internal 2kΩ resistor, and a
42 kΩ resistor in parallel with the external impedance at the CS pin. The ramp current also flows through the
external impedance connected to the CS pin and thus, the amount of slope compensation can be adjusted by
varying the external circuit at the CS pin.
The output of the PWM comparator provides the pulse width information to the output drivers. This comparator is
optimized for speed in order to achieve minimum controllable duty cycles. The comparator’s output duty cycle is
0% for V
COMP
≤1.5V, and increases as V
COMP
increases.
If either Soft-start pin is pulled low (internally or externally) the corresponding COMP pin is pulled down with it,
forcing the output duty cycle to zero. When the Soft-start pin voltage increases, the COMP pin is allowed to
increase. An internal 5 kΩ resistor connected from COMP to an internal 5.0V supply provides a pull-up for the
COMP pin and bias current to the collector of the opto-coupler transistor.
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