Datasheet
Drivers Off
UVLO
Disable
UVLO
7.6V/6.2V
THERMAL
SHUTDOWN
Max
.
Duty
Cycle Limiter
20PA
V
PWR
V
CC
V
CC
1.25V
R
1
R
2
LM5032
LM5032
www.ti.com
SNVS344A –MARCH 2005–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The LM5032 contains all the features necessary to implement two independently regulated current mode dc/dc
converters, or a single high current converter comprised of two parallel interleaved channels using the Forward
converter topology. The two controllers operate 180° out of phase from a common oscillator, thereby reducing
input ripple current. Each regulator channel contains a complete PWM controller, current sense input, soft-start
circuit, and gate driver output. Common to both channels are the startup and V
CC
regulator, line under-voltage
lockout, 2 MHz capable oscillator, maximum duty cycle control, and the hiccup mode fault protection circuit.
The gate driver outputs (OUT1, OUT2) are designed to drive N-channel MOSFETs. Their compound
configuration reduces the turn-off-time, thereby reducing switching losses. Additional features include thermal
shutdown, slope compensation, and the oscillator synchronization capability.
Line Under-Voltage Lock Out, UVLO, Shutdown
The LM5032 contains a line under-voltage lockout circuit (UVLO) designed to enable the V
CC
regulator and
output drivers when the system voltage (V
PWR
) exceeds the desired level (see Figure 17). V
PWR
is the voltage
normally applied to the transformer primary, and usually connected to the VIN pin (see the schematic on Page
1). The threshold at the UVLO comparator is 1.25V. An external resistor divider connected from V
PWR
to ground
provides 1.25V at the UVLO pin when V
PWR
is increased to the desired turn-on threshold. When V
PWR
is below
the threshold the V
CC
regulator and output drivers are disabled, and the internal 20 µA current source is off.
When V
PWR
reaches the threshold, the comparator output switches low to enable the internal circuits and the 20
µA current source. The 20 µA flows into the external divider’s junction, raising the voltage at UVLO, thereby
providing hysteresis. Internally the voltage at UVLO also drives the Maximum Duty Cycle Limiter circuit
(described below), which may influence the values chosen for the UVLO pin resistors. At maximum V
PWR
, the
voltage at UVLO should not exceed 6V. Refer to the Applications Information section for a procedure to calculate
the resistors values.
The LM5032 controller can be shutdown by forcing the UVLO pin below 1.25V with an external switch. When the
UVLO pin is low, the outputs and the V
CC
regulator are disabled, and the LM5032 enters a low power mode. If
VCC pin is not powered from an external source, the current into VIN drops to a nominal 500 µA. If the VCC pin
is powered from an external source, the current into VIN is nominally 50 µA, and the current into the VCC pin is
approximately 4.3 mA. To disable one regulator without affecting the other, see the description of the Soft-start
section.
Figure 17. Drivers Off and V
CC
Disable
Startup Regulator, VIN, VCC
The high voltage startup regulator is integral to the LM5032. The input pin VIN can be connected directly to a
voltage between 13V and 100V, with transient capability to 105V. The startup regulator provides bias voltages to
the series pass V
CC
regulator and the UVLO circuit. The V
CC
regulator is disabled until the voltage at the UVLO
pin (described above) exceeds 1.25V. For applications where V
PWR
exceeds 100V the internal startup regulator
can be powered from an external startup regulator or other available low voltage source. See the Applications
Information section for details.
The V
CC
under-voltage threshold circuit (UVT) monitors the VCC regulator output. When the series pass
regulator is enabled and the internal V
CC
voltage increases to > 7.6V, the UVT comparator activates the PWM
controller and output drivers via the Drivers Off signal. The UVT comparator has built-in hysteresis, with the lower
threshold nominally set to 6.2V. See Figure 4 and Figure 17.
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