Datasheet

LOGIC
V
IN
V
CC
REF
SS
SOFT-STOP
(50 PA)
RT
PGND
AGND
5V
REFERENCE
OSCILLATOR
AND
DUTY CYCLE
LIMITER
DEADTIME
OR
OVERLAP
CONTROL
CLK
CS
TIME
0.5V
PWM
5k
5V
1.4V
R
S
Q
SS
SLOPE COMP
RAMP
V
CC
UVLO
7.6V BIAS
REGULATOR
OUT_A
DRIVER
V
CC
OUT_B
DRIVER
COMP
RESTART
DELAY
(1 PA)
SS
SYNC
UVLO
HYSTERESIS (20 PA)
1.25V
R
2R
2k
RES
CURRENT LIMIT
RESTART
TIMER
&
SS CONTROL
CURRENT
LIMIT
45 PA
0
DCL
SHUTDOWN
0.4V/0.3V
STANDBY
1 : 1
THERMAL
LIMIT
CURRENT
LIMITING
(10 PA)
SOFT-START
(50 PA)
5V
5V
5V
NOT
CURRENT
LIMITING
(10 PA)
V
CC
OUT_A + LEB
LM5026
www.ti.com SNVS363D –AUGUST 2005–REVISED APRIL 2013
PIN DESCRIPTIONS (continued)
Pin Name Description Application Information
EP Exposed Pad Exposed Pad, underside of Connect to system ground plane for reduced thermal resistance.
(WSON WSON package
Package Only)
Block Diagram
Figure 4. Simplified Block Diagram
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM5026