Datasheet

t3 =
50 PA
C
SS
x 3.5V
= 7 x 10
4
x C
SS
t2 =
1 PA
C
SS
x 1.4V
= 1.4 x 10
6
x C
SS
LM5026
www.ti.com SNVS363D –AUGUST 2005–REVISED APRIL 2013
The cool down time, t2 is set by the soft-start capacitor (C
SS
) and the internal 1 µA SS current source, and is
equal to:
(9)
If C
SS
= 0.01 µF, t2 is ≈14 ms.
The soft-start time t3 is set by the internal 50 µA current source, and is equal to:
(10)
The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or
short circuit. This results in lower average input current and lower power dissipated within the power
components. It is recommended that the ratio of t2/(t1 + t3) be in the range of 5 to 10 to make good use of this
feature. If the application requires no delay from the first detection of a current limit condition to the onset of the
hiccup mode (t1 = 0), the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup
mode current limit operation, the RES pin should be connected to ground (AGND).
SOFT-START (SS)
An internal current source and an external soft-start capacitor determines the time required for the output duty
cycle to increase from zero to its final value for regulation. The minimum acceptable time is dependent on the
output capacitance and the response of the feedback loop. If the soft-start time is too quick, the output could
overshoot its intended voltage before the feedback loop can regulate the PWM controller. After power is applied
and the controller is fully enabled, the voltage at the SS pin ramps up as C
SS
is charged by an internal 50 µA
current source. The voltage at the output of the COMP pin current mirror is clamped to the same potential as the
SS pin by a voltage buffer with a sink-only output stage. When the SS voltage reaches ≈1.4V, PWM pulses
appear at the driver output with very low duty cycle. The PWM duty cycle gradually increases as the voltage at
the SS pin charges to ≈5.0V.
VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE
As the input source V
PWR
increases the voltage at the UVLO pin increases proportionately. To limit the Volt x
Seconds applied to the transformer, the maximum allowed PWM duty cycle decreases as the UVLO voltage
increases. If it is desired to increase the slope of the voltage limited duty cycle characteristic, two possible
configurations are shown in Figure 33. After the LM5026 is enabled, the zener diode causes the UVLO pin
voltage to increase more rapidly with increasing input voltage (V
PWR
). The voltage dependent maximum duty
cycle clamp varies with the UVLO pin voltage according to the following equation:
Voltage-Dependent Duty Cycle (%) = 107 - 21.8 X UVLO (11)
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