Datasheet
UVLO
CS
RES
TIME
REF
VCC
OUT_A
VIN
RT
COMP
SS
AGND
PGND
OUT_B
SYNC
DCL
14
13
12
11
10
8
15
16
1
2
3
4
5
7
6
9
VIN
VCC
RES
REF
CS
UVLO
OUT_A
TIME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYNC
COMP
DCL
PGND
RT
SS
OUT_B
AGND
EP
LM5026
SNVS363D –AUGUST 2005–REVISED APRIL 2013
www.ti.com
Connection Diagram
Figure 2. 16-Lead TSSOP Figure 3. 16-Lead WSON
PIN DESCRIPTIONS
Pin Name Description Application Information
1 VIN Input Voltage Source Input to the Start-up Regulator. Operating input range is 13V to 100V with
transient capability to 105V. For power sources outside of this range, the
LM5026 can be biased directly at VCC by an external regulator.
2 UVLO Line Under-Voltage Lockout An external voltage divider from the power source sets the shutdown and
standby comparator levels. When UVLO reaches the 0.4V threshold the VCC
and REF regulators are enabled. At the 1.25V threshold the SS pin is released
and the device enters the active mode.
3 CS Current Sense input for current If CS exceeds 0.5V the output pulse will be terminated, entering cycle-by-cycle
mode control and current limit current limit. An internal switch holds CS low for 100nS after OUT_A switches
high to blank leading edge transients.
4 RES Restart Timer If cycle-by-cycle current limit is reached during any cycle, a 10uA current is
sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5V,
the soft-start capacitor will be fully discharged and then released with a pull-up
current of 1uA. After the first output pulse at OUT_A (when SS =1.4V), the SS
pin charging current will revert back to 50 µA.
5 TIME Gate Drive Overlap or Deadtime An external resistor (RSET) sets either the overlap time or deadtime for the
Control active clamp output. An RSET resistor connected between TIME and AGND
produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor
connected between TIME and REF produces out-of-phase OUT_A and OUT_B
pulses with deadtime.
6 REF Output of 5V Reference Maximum output current is 10mA. Locally decouple with a 0.1µF capacitor.
7 VCC Output of the high voltage start- If an auxiliary winding raises the voltage on this pin above the regulation
up regulator. The VCC voltage setpoint, the internal start-up regulator will shutdown, thus reducing the IC
is regulated to 7.6 V. power dissipation.
8 OUT_A Main Output Driver Output of the main switch PWM gate driver. Capable of 3A peak sink current.
9 OUT_B Active Clamp Output Driver Output of the active clamp switch gate driver. Capable of 0.5A peak source and
sink current.
10 PGND Power Ground Connect directly to Analog Ground
11 AGND Analog Return Connect directly to Power Ground.
12 SS Soft-start An external capacitor and an internal 50 µA current source set the soft-start
ramp. The SS current source is reduced to 1 µA following a restart event. The
soft-stop discharge current is 50 µA.
13 COMP Input to the Pulse Width The external opto-coupler connected to the COMP pin sources current into an
Modulator internal NPN current mirror. The PWM duty cycle is maximum with zero input
current, while 1mA reduces the duty cycle to zero. The current mirror improves
the frequency response by reducing the ac voltage across the opto-coupler
detector.
14 RT Oscillator Frequency Control Normally biased at 2V. The total external resistance connected between RT and
AGND sets the internal oscillator frequency.
15 SYNC Oscillator Synchronization The internal oscillator can be synchronized to an external clock with an external
Input/Output pull-down device. Multiple LM5026 devices can be synchronized together by
connection of their SYNC pins.
16 DCL Maximum Duty Cycle Control An external resistor divider connected from RT to AGND sets the maximum
output duty cycle for OUT_A.
2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5026