Datasheet

OUT_A
OUT_B
OUT_A
OUT_B
K1 * R
SET
N-Channel Active Clamp
(R
SET
to REF)
P-Channel Active Clamp
(R
SET
to GND)
K2 * R
SET
K1 * R
SET
K2 * R
SET
LM5026
www.ti.com SNVS363D –AUGUST 2005–REVISED APRIL 2013
PWM Outputs
The relative phase of the main switch gate driver OUT_A and active clamp gate driver OUT_B can be configured
for multiple applications. For active clamp configurations utilizing a ground referenced P-Channel clamp switch,
the two outputs should be in phase, with the active clamp output overlapping the main output. For active clamp
configurations utilizing a high side N-Channel switch, the active clamp output should be out of phase with main
output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the
LM5026 is the ability to accurately configure either deadtime (both off) or overlap time (both on) of the gate driver
outputs. The overlap / deadtime magnitude is controlled by the resistor value (RSET) connected to the TIME pin
of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or to
AGND for overlap control. The internal configuration detector senses the direction of current flow in the TIME pin
resistor and configures the phase relationship of the main and active clamp outputs.
Figure 18. PWM Output Phasing / Timing
The rising edge overlap or deadtime and the falling edge overlap or deadtime are identical and are independent
of operating frequency or duty cycle. The magnitude of the overlap/deadtime can be calculated as follows:
Overlap Time = 2.8 x R
SET
+ 2
where
• R
SET
in kΩ
• overlap is in ns (1)
.
Deadtime = 2.9 x R
SET
+ 14
where
• R
SET
in kΩ
• deadtime is in ns (2)
Gate Driver Outputs
The LM5026 provides two gate driver outputs, the main power switch control (OUT_A) and the active clamp
switch control (OUT_B). The main gate driver features a compound configuration, consisting of both MOS and
bipolar devices, which provide superior gate drive characteristics. The bipolar device provides most of the drive
current capability and sinks a relatively constant current, which is ideal for driving large power MOSFETs. As the
switching event nears conclusion and the bipolar device saturates, the internal MOS device provides a low
impedance to compete the switching event.
During turn-off at the Miller plateau region, typically between 2V - 4V, the voltage differential between the output
and PGND is small and the current source characteristic of the bipolar device is beneficial to reduce the
transition time. During turn-on, the resistive characteristics of a purely MOS gate driver is adequate since the
supply to output voltage differential is fairly large in the Miller region.
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