Datasheet

CS2
SS
20 PA
1 PA
LM5025
www.ti.com SNVS265B –DECEMBER 2003–REVISED MARCH 2013
Figure 15. Current Limit
Oscillator and Sync Capability
The LM5025 oscillator is set by a single external resistor connected between the RT pin and GND. To set a
desired oscillator frequency (F), the necessary RT resistor can be calculated from:
RT = (5725/F)
1.026
where
• F is in kHz
• RT in kΩ (3)
The RT resistor should be located very close to the device and connected directly to the pins of the IC (RT and
GND).
A unique feature of LM5025 is the ability to synchronize the oscillator to an external clock with a frequency that is
either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is
80% of the free running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A
minimum pulse width of 100ns is required for the synchronization clock . If the synchronization feature is not
required, the SYNC pin should be connected to GND to prevent any abnormal interference . The internal
oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal will act
directly as the master clock for the controller. Both the frequency and the maximum duty cycle of the PWM
controller can be controlled by the SYNC signal (within the limitations of the Volt x Second Clamp). The
maximum duty cycle (D) will be (1-D) of the SYNC signal.
Feed-Forward Ramp
An external resistor (R
FF
) and capacitor (C
FF
) connected to V
IN
and GND are required to create the PWM ramp
signal. The slope of the signal at the RAMP pin will vary in proportion to the input line voltage. This varying slope
provides line feedforward information necessary to improve line transient response with voltage mode control.
The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to
control the duty cycle of the main switch output. The Volt Second Clamp comparator also monitors the RAMP pin
and if the ramp amplitude exceeds 2.5V the present cycle is terminated. The ramp signal is reset to GND at the
end of each cycle by either the internal clock or the Volt Second comparator,which ever occurs first.
Soft-start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing start-up stresses and surges. At power on, a 20µA current is sourced out of the softstart pin (SS) into
an external capacitor. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and therefore
the PWM duty cycle. In the event of a fault as determined by V
CC
undervoltage, line undervoltage (UVLO) or
second level current limit, the output gate drivers are disabled and the softstart capacitor is fully discharged.
When the fault condition is no longer present a softstart sequence will be initiated. Following a second level
current limit detection (CS2), the softstart current source is reduced to 1µA until the first output pulse is
generated by the PWM comparator. The current source returns to the nominal 20µA level after the first output
pulse (~1V at the SS pin).
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