Datasheet

LOGIC
V
IN
REF
SS
90 PA
RT
LOGIC
PGND
AGND
5V
REFERENCE
OSCILLATOR
CLK
CS1
TIME
0.5V
0.5V
PWM
5k
5V
1V
R
S
Q
Q
SS
FF RAMP
CS2
RAMP
SLOPE D TO V
IN
CLK + LEB
7.6V SERIES
REGULATOR
OUT_B
DRIVER
V
CC
COMP
SS
SS Amp
(Sink Only)
MAX V*S
CLAMP
SYNC
UVLO
HYSTERESIS
(20 PA)
2.5V
+
-
UVLO
+
-
OUT_A
DRIVER
V
CC
V
CC
V
CC
UVLO
2.5V
89 PA
DEADTIME
OR
OVERLAP
CONTROL
+
-
+
-
+
-
ENABLE
OUTPUTS
LM5025C
SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013 www.ti.com
PIN DESCRIPTIONS (continued)
Pin Name Description Application Information
15 SYNC Oscillator UP/DOWN synchronization input The internal oscillator can be synchronized to an external
clock with a frequency 20% lower than the internal
oscillator’s free running frequency. There is no constraint
on the maximum sync frequency.
16 UVLO Line Under-Voltage shutdown An external voltage divider from the power source sets the
shutdown comparator levels. The comparator threshold is
2.5V. Hysteresis is set by an internal current source (20
µA) that is switched on or off as the UVLO pin potential
crosses the 2.5V threshold.
Block Diagram
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