Datasheet

RAMP
CS1
CS2
TIME
REF
V
CC
OUT_A
V
IN
RT
COMP
SS
AGND
PGND
OUT_B
SYNC
UVLO
14
13
12
11
10
8 9
15
16
1
2
3
4
5
7
6
LM5025C
www.ti.com SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
Connection Diagram
Figure 2. 16-Lead TSSOP
Package Number PW0016A
PIN DESCRIPTIONS
Pin Name Description Application Information
1 V
IN
Source Input Voltage Input to start-up regulator. Input range 13V to 90V, with
transient capability to 105V.
2 RAMP Modulator ramp signal An external RC circuit from Vin sets the ramp slope. This
pin is discharged at the conclusion of every cycle by an
internal FET, initiated by either the internal clock or the
V*Sec Clamp comparator.
3 CS1 Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.5V the outputs will go into Cycle-by-
Cycle current limit. CS1 is held low for 50ns after OUT_A
switches high providing leading edge blanking.
4 CS2 Current sense input for soft restart If CS2 exceeds 0.5V the outputs will be disabled and a
softstart commenced. The soft-start capacitor will be fully
discharged and then released with a pull-up current of
1µA. After the first output pulse (when SS =1V), the SS
charge current will revert back to 90 µA.
5 TIME Output overlap/Deadtime control An external resistor (R
SET
) sets either the overlap time or
dead time for the active clamp output. An R
SET
resistor
connected between TIME and GND produces in-phase
OUT_A and OUT_B pulses with overlap. An R
SET
resistor
connected between TIME and REF produces out-of-phase
OUT_A and OUT_B pulses with deadtime.
6 REF Precision 5 volt reference output Maximum output current: 10 mA Locally decouple with a
0.1 µF capacitor. Reference stays low until the V
CC
UV
comparator is satisfied.
7 V
CC
Output from the internal high voltage start-up If an auxiliary winding raises the voltage on this pin above
regulator. The V
CC
voltage is regulated to 7.6V. the regulation setpoint, the internal start-up regulator will
shutdown, reducing the IC power dissipation.
8 OUT_A Main output driver Output of the main switch PWM output gate driver. Output
capability of 3A peak sink current.
9 OUT_B Active Clamp output driver Output of the Active Clamp switch gate driver. Capable of
1.25A peak sink current..
10 PGND Power ground Connect directly to analog ground.
11 AGND Analog ground Connect directly to power ground.
12 SS Soft-start control An external capacitor and an internal 90 µA current source
set the softstart ramp. The SS current source is reduced to
1 µA initially following a CS2 over-current event or an over
temperature event.
13 COMP Input to the Pulse Width Modulator An internal 5 kΩ resistor pull-up is provided on this pin.
The external opto-coupler sinks current from COMP to
control the PWM duty cycle.
14 RT Oscillator timing resistor pin An external resistor connected from RT to ground sets the
internal oscillator frequency.
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