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LM5025C

www.ti.com

SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013

LM5025C Active Clamp Voltage Mode PWM Controller

Check for Samples: LM5025C

FEATURES

DESCRIPTION

The LM5025C is a functional variant of the LM5025

• Internal Start-Up Bias Regulator

active clamp PWM controller. The functional

• 3A Compound Main Gate Driver

differences of the LM5025C are: The maximum duty

• Programmable Line Under-Voltage Lockout

cycle of the LM5025C is increased from 80% to 91%.

(UVLO) with Adjustable Hysteresis

The soft-start capacitor charging current is increased

from 20 µA to 90 µA. The V

regulator current limit

• Voltage Mode Control with Feed-Forward

threshold is increased from 25 mA to 55 mA. The

• Adjustable Dual Mode Over-Current Protection

CS1 and CS2 current limit thresholds have been

• Programmable Overlap or Deadtime between

increased to 0.5V. The internal CS2 filter discharge

the Main and Active Clamp Outputs

device has been disabled and no longer operates

each clock cycle. The internal V

and V

REF

• Volt x Second Clamp

regulators continue to operate when the line UVLO

• Programmable Soft-start

pin is below threshold.

• Leading Edge Blanking

The LM5025C PWM controller contains all of the

• Single Resistor Programmable Oscillator

features necessary to implement power converters

• Oscillator UP / DOWN Sync Capability

utilizing the Active Clamp / Reset technique. With the

active clamp technique, higher efficiencies and

• Precision 5V Reference

greater power densities can be realized compared to

• Thermal Shutdown

conventional catch winding or RDC clamp / reset

techniques. Two control outputs are provided, the

PACKAGE

main power switch control (OUT_A) and the active

clamp switch control (OUT_B). The two internal

• TSSOP-16

compound gate drivers parallel both MOS and Bipolar

devices, providing superior gate drive characteristics.

This controller is designed for high-speed operation

including an oscillator frequency range up to 1MHz

and total PWM and current sense propagation delays

less than 100 ns. The LM5025C includes a high-

voltage start-up regulator that operates over a wide

input range of 13V to 90V. Additional features

include: Line Under Voltage Lockout (UVLO),

softstart, oscillator UP/DOWN sync capability,

precision reference and thermal shutdown.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 LM5025C Active Clamp Voltage Mode PWM Controller Check for Samples: LM5025C FEATURES DESCRIPTION • • • The LM5025C is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025C are: The maximum duty cycle of the LM5025C is increased from 80% to 91%. The soft-start capacitor charging current is increased from 20 µA to 90 µA.
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LM5025C SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Application Circuit VOUT 3.3V VIN 35V - 78V LM5025C CS1 VIN UVLO VCC ERROR AMP and ISOLATION OUT_A OUT_B RAMP COMP REF CS2 SYNC Rt TIME SS PGND AGND UP/DOWN SYNC Figure 1.
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LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 Connection Diagram VIN 1 16 UVLO RAMP 2 15 SYNC CS1 3 14 RT CS2 4 13 COMP TIME 5 12 SS REF 6 11 AGND VCC 7 10 PGND OUT_A 8 9 OUT_B Figure 2. 16-Lead TSSOP Package Number PW0016A PIN DESCRIPTIONS Pin Name Description Application Information 1 VIN Source Input Voltage Input to start-up regulator. Input range 13V to 90V, with transient capability to 105V.
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LM5025C SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name 15 SYNC Oscillator UP/DOWN synchronization input Description The internal oscillator can be synchronized to an external clock with a frequency 20% lower than the internal oscillator’s free running frequency. There is no constraint on the maximum sync frequency.
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LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 105V VCC to GND -0.3V to 16V CS1, CS2 to GND -0.3 to 1.00V All other inputs to GND -0.
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LM5025C SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 32 kΩ, RSET = 27.4 kΩ) unless otherwise stated (1) Symbol CS2 Prop Parameter CS2 Delay to Output Conditions Cycle by Cycle Threshold Voltage (CS1) Cycle Skip Threshold Voltage (CS2) Min CS2 Step from 0 to 0.
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LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 32 kΩ, RSET = 27.
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LM5025C SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VCC Regulator Start-up Characteristics, VCC vs Vin VCC vs ICC 10 16 VIN 14 8 12 VCC (V) VCC (V) 10 VCC 8 6 6 4 4 2 2 0 0 0 2 4 6 8 10 12 14 0 16 20 30 40 50 60 ICC (mA) VIN (V) Figure 3. Figure 4. VREF vs IREF Oscillator Frequency vs RT 6 5 VREF (V) 4 3 2 1 0 0 5 10 15 20 25 IREF (mA) Figure 5. Figure 6.
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LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Dead Time vs Temperature RSET = 29.5K Dead Time vs RSET 140 400 350 130 DEADTIME (ns) DEADTIME (ns) 300 250 200 150 120 110 100 100 90 50 0 0 20 40 60 80 100 80 -40 120 RSET (k:) 25 75 125 o TEMPERATURE ( C) Figure 9. Figure 10. SS Pin Current vs Temperature Figure 11.
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LM5025C SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com DETAILED OPERATING DESCRIPTION The LM5025C is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025C are: The maximum duty cycle of the LM5025C is increased from 80% to 91%. The soft-start capacitor charging current is increased from 20 µA to 90 µA. The VCC regulator current limit threshold is increased from 25 mA to 55 mA. The CS1 and CS2 current limit thresholds have been increased to 0.
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LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 PWM Outputs The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific application. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two outputs should be in phase with the active clamp output overlapping the main output.
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LM5025C SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com PWM Comparator The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The internal 5kΩ pull-up resistor, connected between the internal 5V reference and COMP, can be used as the pull-up for an optocoupler. The comparator polarity is such that 0V on the COMP pin will produce a zero duty cycle on both gate driver outputs.
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LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve dynamic performance. This same FET remains on an additional 50ns at the start of each main switch cycle to attenuate the leading edge spike in the current sense signal.
PAGE 14
LM5025C SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 www.ti.com Soft-Start The softstart feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. At power on, a 90 µA current is sourced out of the softstart pin (SS) into an external capacitor. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and therefore the PWM duty cycle.
PAGE 15
LM5025C www.ti.com SNVS568C – SEPTEMBER 2008 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5025CMTCE/NOPB TSSOP PW 16 250 178.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM5025CMTCX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5025CMTCE/NOPB TSSOP PW LM5025CMTCX/NOPB TSSOP PW 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.
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