Datasheet

LM5025A
www.ti.com SNVS293E –DECEMBER 2004–REVISED MARCH 2013
Table 1. PIN DESCRIPTION (continued)
Pin Name Description Application Information
3 CS1 Current sense input for cycle-by- If CS1 exceeds 0.5V the outputs will go into Cycle-by-Cycle current
cycle limiting limit. CS1 is held low for 50ns after OUT_A switches high providing
leading edge blanking.
4 CS2 Current sense input for soft restart If CS2 exceeds 0.5V the outputs will be disabled and a softstart
commenced. The soft-start capacitor will be fully discharged and then
released with a pull-up current of 1µA. After the first output pulse (when
SS =1V), the SS charge current will revert back to 20µA.
5 TIME Output overlap/Deadtime control An external resistor (R
SET
) sets either the overlap time or dead time for
the active clamp output. An R
SET
resistor connected between TIME and
GND produces in-phase OUT_A and OUT_B pulses with overlap. An
R
SET
resistor connected between TIME and REF produces out-of-
phase OUT_A and OUT_B pulses with deadtime.
6 REF Precision 5 volt reference output Maximum output current: 10mA Locally decouple with a 0.1µF
capacitor. Reference stays low until the V
CC
UV comparator is satisfied.
7 V
CC
Output from the internal high If an auxiliary winding raises the voltage on this pin above the
voltage start-up regulator. The V
CC
regulation setpoint, the internal start-up regulator will shutdown,
voltage is regulated to 7.6V. reducing the IC power dissipation.
8 OUT_A Main output driver Output of the main switch PWM output gate driver. Output capability of
3A peak sink current.
9 OUT_B Active Clamp output driver Output of the Active Clamp switch gate driver. Capable of 1.25A peak
sink current..
10 PGND Power ground Connect directly to analog ground.
11 AGND Analog ground Connect directly to power ground. For the WSON package option the
exposed pad is electrically connected to AGND.
12 SS Soft-start control An external capacitor and an internal 20µA current source set the
softstart ramp. The SS current source is reduced to 1uA initially
following a CS2 over-current event or an over temperature event.
13 COMP Input to the Pulse Width Modulator An internal 5kΩ resistor pull-up is provided on this pin. The external
opto-coupler sinks current from COMP to control the PWM duty cycle.
14 RT Oscillator timing resistor pin An external resistor connected from RT to ground sets the internal
oscillator frequency.
15 SYNC Oscillator UP/DOWN The internal oscillator can be synchronized to an external clock with a
synchronization input frequency 20% lower than the internal oscillator’s free running
frequency. There is no constraint on the maximum sync frequency.
16 UVLO Line Under-Voltage shutdown An external voltage divider from the power source sets the shutdown
comparator levels. The comparator threshold is 2.5V. Hysteresis is set
by an internal current source (20µA) that is switched on or off as the
UVLO pin potential crosses the 2.5V threshold.
- EP Exposed pad, underside of the Internally bonded to the die substrate. Connect to GND potential for low
WSON package option thermal impedance.
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