Datasheet

RAMP
CS1
CS2
TIME
REF
V
CC
OUT_A
V
IN
RT
COMP
SS
AGND
PGND
OUT_B
SYNC
UVLO
14
13
12
11
10
8 9
15
16
1
2
3
4
5
7
6
LM5025A
UVLO
PGND
AGND
COMP
OUT_A
OUT_B
V
CC
SS
Rt
SYNC
REF
TIME
RAMP
CS1
V
IN
V
IN
35 - 78V
V
OUT
3.3V
UP/DOWN
SYNC
ERROR
AMP &
ISOLATION
CS2
LM5025A
SNVS293E –DECEMBER 2004–REVISED MARCH 2013 www.ti.com
Typical Application Circuit
Figure 1. Simplified Active Clamp Forward Power Converter
Connection Diagram
Figure 2. 16-Lead TSSOP, WSON
Table 1. PIN DESCRIPTION
Pin Name Description Application Information
1 V
IN
Source Input Voltage Input to start-up regulator. Input range 13V to 90V, with transient
capability to 105V.
2 RAMP Modulator ramp signal An external RC circuit from Vin sets the ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET, initiated
by either the internal clock or the V*Sec Clamp comparator.
2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
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