Datasheet

LM5025A
SNVS293E –DECEMBER 2004–REVISED MARCH 2013 www.ti.com
PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is
optimized for speed in order to achieve minimum controllable duty cycles. The internal 5kΩ pull-up resistor,
connected between the internal 5V reference and COMP, can be used as the pull-up for an optocoupler. The
comparator polarity is such that 0V on the COMP pin will produce a zero duty cycle on both gate driver outputs.
Volt Second Clamp
The Volt x Second Clamp comparator compares the ramp signal (RAMP) to a fixed 2.5V reference. By proper
selection of RFF and CFF, the maximum ON time of the main switch can be set to the desired duration. The ON
time set by Volt x Second Clamp varies inversely with the line voltage because the RAMP capacitor is charged
by a resistor connected to Vin while the threshold of the clamp is a fixed voltage (2.5V). An example will illustrate
the use of the Volt x Second Clamp comparator to achieve a 50% duty cycle limit, at 200KHz, at a 48V line input:
A 50% duty cycle at a 200KHz requires a 2.5µs of ON time. At 48V input the Volt x Second product is 120V x µs
(48V x 2.5µs). To achieve this clamp level:
R
FF
x C
FF
= V
IN
x T
ON
/ 2.5V (1)
48 x 2.5µ / 2.5 = 48µ (2)
Select C
FF
= 470pF
R
FF
= 102kΩ
The recommended capacitor value range for CFF is 100pF to 1000pF.
The C
FF
ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled
by either the internal clock or by the V x S Clamp comparator, whichever event occurs first.
Current Limit
The LM5025A contains two modes of over-current protection. If the sense voltage at the CS1 input exceeds 0.5V
the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input exceeds
0.5V, the controller will terminate the present cycle, discharge the softstart capacitor and reduce the softstart
current source to 1µA. The softstart (SS) capacitor is released after being fully discharged and slowly charges
with a 1µA current source. When the voltage at the SS pin reaches approximately 1V, the PWM comparator will
produce the first output pulse at OUT_A. After the first pulse occurs, the softstart current source will revert to the
normal 20µA level. Fully discharging and then slowly charging the SS capacitor protects a continuously over-
loaded converter with a low duty cycle hiccup mode.
These two modes of over-current protection allow the user great flexibility to configure the system behavior in
over-load conditions. If it is desired for the system to act as a current source during an over-load, then the CS1
cycle-by-cycle current limiting should be used. In this case the current sense signal should be applied to the CS1
input and the CS2 input should be grounded. If during an overload condition it is desired for the system to briefly
shutdown, followed by softstart retry, then the CS2 hiccup current limiting mode should be used. In this case the
current sense signal should be applied to the CS2 input and the CS1 input should be grounded. This shutdown /
soft-start retry will repeat indefinitely while the over-load condition remains. The hiccup mode will greatly reduce
the thermal stresses to the system during heavy overloads. The cycle-by-cycle mode will have higher system
thermal dissipations during heavy overloads, but provides the advantage of continuous operation for short
duration overload conditions.
It is possible to utilize both over-current modes concurrently, whereby slight overload conditions activate the CS1
cycle-by-cycle mode while more severe overloading activates the CS2 hiccup mode. Generally the CS1 input will
always be configured to monitor the main switch FET current each cycle. The CS2 input can be configured in
several different ways depending upon the system requirements.
• The CS2 input can also be set to monitor the main switch FET current except scaled to a higher threshold
than CS1
• An external over-current timer can be configured which trips after a pre-determined over-current time, driving
the CS2 input high, initiating a hiccup event.
• In a closed loop voltage regulaton system, the COMP input will rise to saturation when the cycle-by-cycle
current limit is active. An external filter/delay timer and voltage divider can be configured between the COMP
pin and the CS2 pin to scale and delay the COMP voltage. If the CS2 pin voltage reaches 0.5V a hiccup
event will initiate.
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