Datasheet

1
2
3
4 5
6
7
8
CS
GND
OUT
VCC
COMP
SS
VSD
QR
LM5023
www.ti.com SNVS961D –APRIL 2013–REVISED JANUARY 2014
PIN FUNCTIONS
NAME NO. TYPE DESCRIPTION
Control input for the Pulse Width Modulator and Skip cycle comparators.
COMP 4 I COMP pull-up is provided by an internal 42 K resistor which may be
used to bias an opto-coupler transistor.
Current sense input for current mode control and over-current protection.
Current limiting is accomplished using a dedicated current sense
CS 5 I comparator. If the CS comparator input exceeds 0.5 V, the OUT pin
switches low for cycle-by-cycle current limit. CS is held low for 90 ns
after OUT switches high to blank the leading edge current spike.
GND 6 G Ground connection return for internal circuits.
High current output to the external MOSFET gate input with source/sink
OUT 7 O
current capability of 0.3 A and 0.7 A respectively.
The auxiliary FLYBACK winding of the power transformer is monitored to
detect the Quasi-Resonant operation. The peak auxiliary voltage is
QR 1 I
sensed to detect an output overvoltage (OVP) fault and shuts down the
controller.
An external capacitor and an internal 22 µA current source sets the soft-
SS 3 O
start ramp.
Connect this pin to the Gate of the external start-up circuit FET; it will
VSD 2 O
disable the start-up FET after VCC is valid.
VCC provides bias to controller and gate drive sections of the LM5023.
VCC 8 P
An external capacitor must be connected from this pin to ground.
DEVICE INFORMATION
LM5023 Pin Configuration
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