Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

( )

Freq :

n (Vo Vf Vin

Lp 2 Pout tdly

Vin n Vo Vf

é ù

+ +

ê ú

é ù

h +

ë û

ê ú

ë û

g g g

Pout Lp Ipk Freq

= · · · · h

tdly Lp COSS

= · ·

Tp ton toff tdly= + +

LM5023

SNVS961D –APRIL 2013–REVISED JANUARY 2014

www.ti.com

The total switching period is:

The resonant circuit created by the transformer primary inductance and the MOSFETs output capacitance is the

tdly time, refer to Figure 11.

Combining equations:

From inspection of the equations, it can be seen that the QR Flyback converter does not operate at a fixed

frequency. The frequency varies with the output load, input line voltage, or a combination of the two. In order to

keep LM5023 frequency below the EMI starting limit of 150 kHz per CISPR--22, the LM5023 has an internal

timer which prevents the output drive from restarting within 7.69 μs of the previous driver output (OUT) high to

low transition. This timer clamps the maximum switching frequency from exceeding 130 kHz (typical).

PWM Comparator

The PWM comparator compares the current sense signal with the loop error voltage from the COMP pin. The

COMP pin voltage is reduced by a fixed 0.75 V offset and then attenuated by a 3:1 resistor divider. The PWM

comparator input offset voltage is designed such that less than 0.75 V at the COMP pin will result in a zero duty

cycle at the controller output.

Soft-Start

The soft-start feature allows the power converter to gradually reach the initial steady state operating point,

thereby reducing start-up stresses and current surges. At power on, after the VCC reaches the VCC

threshold

an internal 22 μA current source charges an external capacitor connected to the SS pin. The capacitor voltage

will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output pulses.

Gate Driver

The LM5023 driver (OUT) was designed to drive the gate of an N Channel MOSFET and is capable of sourcing

a peak current of 0.4 A and sinking 0.7 A.

Skip Cycle Operation

During light load conditions, the efficiency of the switching power supply typically drops as the losses associated

with switching and operating bias currents of the converter become a significant percentage of the power

delivered to the load. The largest component of the power loss is the switching loss associated with the gate

driver and external MOSFET gate charge. Each PWM cycle consumes a finite amount of energy as the MOSFET

is turned on and then turned off. These switching losses are proportional to the frequency of operation.

To improve the light load efficiency the LM5023 enters a Skip Cycle mode during light load conditions. As the

output load is decreased, the COMP pin voltage is reduced by the voltage feedback loop to reduce the Flyback

converters peak primary current. Referring to the Block Diagram , the PWM comparator input tracks the COMP

pin voltage through a 0.75 V level shift circuit and a 3:1 resistor divider. As the COMP pin voltage falls, the input

to the PWM comparator falls proportionately. When the PWM comparator input falls to 125 mV, the Skip Cycle

comparator detects the light load condition and disables output pulses from the controller. The LM5023 also

reduces all internal bias currents, while in skip mode, to further reduce quiescent power. The controller continues

to skip switching cycles until the power supply output falls and the COMP pin voltage increases to demand more

output current. The number of cycles skipped will depend on the load and the response time of the frequency

Product Folder Links: LM5023