Datasheet

G
EA
=
=
s x R1 x C2 +1
s x R1 x C1 x C2
C1 + C2
s
+1
Z
F
Z
I
1
R
FB2
(C1 + C2)
x
100 1k 10k 100k 1M
FREQUENCY (Hz)
-180
-120
-60
0
60
120
180
POWER STAGE PHASE (°)
LM5022
SNVS480G –JANUARY 2007–REVISED DECEMBER 2013 www.ti.com
Figure 20. Power Stage Gain and Phase
The single pole causes a roll-off in the gain of -20 dB/decade at lower frequency. The combination of the RHP
zero and sampling double pole maintain the slope out to beyond the switching frequency. The phase tends
towards -90° at lower frequency but then increases to -180° and beyond from the RHP zero and the sampling
double pole. The effect of the ESR zero is not seen because its frequency is several decades above the
switching frequency. The combination of increasing gain and decreasing phase makes converters with RHP
zeroes difficult to compensate. Setting the overall control loop bandwidth to 1/3 to 1/10 of the RHP zero
frequency minimizes these negative effects, but requires a compromise in the control loop bandwidth. If this loop
were left uncompensated, the bandwidth would be 89 kHz and the phase margin -54°. The converter would
oscillate, and therefore is compensated using the error amplifier and a few passive components.
The transfer function of the compensation block, G
EA
, can be derived by treating the error amplifier as an
inverting op-amp with input impedance Z
I
and feedback impedance Z
F
. The majority of applications will require a
Type II, or two-pole one-zero amplifier, shown in Figure 18. The LaPlace domain transfer function for this Type II
network is given by the following:
(52)
Many techniques exist for selecting the compensation component values. The following method is based upon
setting the mid-band gain of the error amplifier transfer function first and then positioning the compensation zero
and pole:
1. Determine the desired control loop bandwidth: The control loop bandwidth, f
0dB
, is the point at which the
total control loop gain (H = G
PS
x G
EA
) is equal to 0 dB. For this example, a low bandwidth of 10 kHz, or
approximately 1/6th of the RHP zero frequency, is chosen because of the wide variation in input voltage.
2. Determine the gain of the power stage at f
0dB
: This value, A, can be read graphically from the gain plot of
G
PS
or calculated by replacing the ‘s’ terms in G
PS
with ‘2πf
0dB
’. For this example the gain at 10 kHz is
approximately 16 dB.
3. Calculate the negative of A and convert it to a linear gain: By setting the mid-band gain of the error
amplifier to the negative of the power stage gain at f
0dB
, the control loop gain will equal 0 dB at that
frequency. For this example, -16 dB = 0.15V/V.
4. Select the resistance of the top feedback divider resistor R
FB2
: This value is arbitrary, however selecting
a resistance between 10 kΩ and 100 kΩ will lead to practical values of R1, C1 and C2. For this example,
R
FB2
= 20 kΩ 1%.
5. Set R1 = A x R
FB2
: For this example: R1 = 0.15 x 20000 = 3 kΩ
6. Select a frequency for the compensation zero, f
Z1
: The suggested placement for this zero is at the low
frequency pole of the power stage, f
LFP
= ωLFP / 2π. For this example, f
Z1
= f
LFP
= 423Hz
7. Set
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