Datasheet

100 1k 10k 100k 1M
FREQUENCY (Hz)
-30
-15
0
15
30
45
60
POWER STAGE GAIN (dB)
1
S
Q
n
=
-D + 0.5 + (1 - D)
S
e
S
n
Z
RHP
=
R
O
x
V
IN
V
O
2
L
LM5022
www.ti.com SNVS480G –JANUARY 2007–REVISED DECEMBER 2013
(47)
The sampling double pole quality factor is:
(48)
The sampling double corner frequency is:
ω
n
= π x f
SW
(49)
The natural inductor current slope is:
S
n
= R
SNS
x V
IN
/ L (50)
The external ramp slope is:
S
e
= 45 µA x (2000 + R
S1
+ R
S2
)] x f
SW
(51)
In the equation for A
PS
, DC gain is highest when input voltage and output current are at the maximum. In this the
example those conditions are V
IN
= 16V and I
O
= 500 mA.
DC gain is 44 dB. The low frequency pole f
P
= 2πω
P
is at 423Hz, the ESR zero f
Z
= 2πω
Z
is at 5.6 MHz, and the
right-half plane zero f
RHP
= 2πω
RHP
is at 61 kHz. The sampling double-pole occurs at one-half of the switching
frequency. Proper selection of slope compensation (via R
S2
) is most evident the sampling double pole. A well-
selected R
S2
value eliminates peaking in the gain and reduces the rate of change of the phase lag. Gain and
phase plots for the power stage are shown in Figure 19.
Figure 19. Power Stage Gain and Phase
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