Datasheet

RT/SYNC
LM5022
EXTERNAL
CLOCK
C
SS
100 pF
120 ns
(Typical)
EXTERNAL
CLOCK
OUT PIN
R
T
15 ns to 150 ns
( )
8
SW
T
11
SW
1 8 10 f
R
f 5.77 10
-
-
- ´ ´
=
´ ´
LM5022
www.ti.com SNVS480G –JANUARY 2007–REVISED DECEMBER 2013
The LM5022 current sense and PWM comparators are very fast, and may respond to short duration noise
pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated
with the CS filter must be located very close to the device and connected directly to the pins of the controller (CS
and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to
the sense resistor and the current sense filter network. The current sense resistor can be located between the
source of the primary power MOSFET and power ground, but it must be a low inductance type. When designing
with a current sense resistor all of the noise sensitive low-power ground connections should be connected
together locally to the controller and a single connection should be made to the high current power ground
(sense resistor ground point).
OSCILLATOR, SHUTDOWN AND SYNC
A single external resistor, R
T
, connected between the RT/SYNC and GND pins sets the LM5022 oscillator
frequency. To set the switching frequency, f
SW
, R
T
can be calculated from:
where
• f
SW
is in Hz
• R
T
is in Ω (1)
The LM5022 can also be synchronized to an external clock. The external clock must have a higher frequency
than the free running oscillator frequency set by the R
T
resistor. The clock signal should be capacitively coupled
into the RT/SYNC pin with a 100 pF capacitor as shown in Figure 14. A peak voltage level greater than 3.8V at
the RT/SYNC pin is required for detection of the sync pulse. The sync pulse width should be set between 15 ns
to 150 ns by the external components. The R
T
resistor is always required, whether the oscillator is free running
or externally synchronized. The voltage at the RT/SYNC pin is internally regulated to 2V, and the typical delay
from a logic high at the RT/SYNC pin to the rise of the OUT pin voltage is 120 ns. R
T
should be located very
close to the device and connected directly to the pins of the controller (RT/SYNC and GND).
Figure 14. Sync Operation
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