Datasheet

+
+
+
V
IN
BST
RON
RTN
SW
VCC
FB
VIN
VOUT
R2
R7
R3
C9
C1
C4
R1
R5
L1
UVLO
C7
LM5019
12V-95V
1
2
3
4
5
6
8
7
(TP4)
+
C5
1 F 0.1 F
127 N
14 N
237 N
GND
(TP1)
(TP2)
UVLO/SD
U1
R6
(TP3)
(TP5)
GND
R4
C6
C8
+
D2
R8
EXP
0
1 N
6.98 N
4.7 F
0
220 H
0.01 F
1 F
3300 pF
0.1 F
46.4 N
(TP6)
SW
R
UV2
V
IN
(UVLO,rising) = 1.225V x
R
UV1
+ 1
( )
V
IN
(HYS)
=
I
HYS
x R
UV2
LM5019
SNVS788E –JANUARY 2012–REVISED DECEMBER 2013 www.ti.com
(14)
and
where
• I
HYS
= 20μA (15)
Setting UVLO hysteresis of 2.5 V and UVLO rising threshold of 12 V results in R
UV1
= 14.53 kΩ and R
UV2
= 125
kΩ. Selecting standard value of R
UV1
= 14 kΩ and R
UV2
= 125kΩ results in UVLO thresholds and hysteresis of
12.4 V and 2.5 V respectively.
Application Circuit: 12 V TO 95 V Input and 10 V, 100 mA Output Buck Converter
The application schematic of a buck supply is shown in Figure 16. For output voltage (V
OUT
) above the maximum
regulation threshold of V
CC
(8.3 V, see Electrical Characteristics), the V
CC
pin can be connected to V
OUT
through
a diode (D2), as shown below, for higher efficiency and lower power dissipation in the IC.
Ripple Configuration
LM5019 uses Constant-On-Time (COT) control scheme, in which the on-time is terminated by an on-timer, and
the off-time is terminated by the feedback voltage (V
FB
) falling below the reference voltage (V
REF
). Therefore, for
stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during
the off-time. Furthermore, this change in feedback voltage (V
FB
) during off-time must be large enough to
suppress any noise component present at the feedback node.
Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output
node (V
OUT
) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses R
r
and C
r
and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using C
ac
to the feedback node (FB). Since this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See application note
AN-1481 for more details for each ripple generation method.
Figure 16. Final Schematic for 12 V to 95 V Input, and 10 V, 100 mA Output Buck Converter
14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LM5019