Datasheet

VCC
To FB
R
FB1
VOUT
R
2
R
1
R
FB2
C
1
D
B
R
FB1
x R
FB2
R
FB1
+ R
FB2
t
S
= C
1
x (R
2
+
)
LM5017
www.ti.com SNVS783G –JANUARY 2012–REVISED DECEMBER 2013
To achieve the desired soft-start, the following design guidance is recommended:
(1) R
2
is selected so that V
FB
is higher than 1.225 V for a V
CC
of 4.5 V, but is lower than 5 V when V
CC
is 8.55 V.
If an external V
CC
is used, V
FB
should not exceed 5 V at maximum V
CC
.
(2) C
1
is selected to achieve the desired start-up time that can be determined as:
(3) R
1
is used to maintain the node B voltage at zero after the soft-start is finished. A value larger than the
feedback resistor divider is preferred.
Based on the schematic shown in Figure 17, selecting C
1
= 1 uF, R
2
= 1 kΩ, R
1
= 30 kΩ results in a soft-start
time of about 2 ms.
Figure 19. Soft-Start Circuit
Layout Recommendation
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. C
IN
: The loop consisting of input capacitor (C
IN
), V
IN
pin, and RTN pin carries switching currents. Therefore,
the input capacitor should be placed close to the IC, directly across V
IN
and RTN pins and the connections to
these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of
input capacitance near the IC. A good practice is to use a 0.1 μF or 0.47 μF capacitor directly across the V
IN
and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 20).
2. C
VCC
and C
BST
: The V
CC
and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area should be minimized (See Figure 20).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of LM5017. Therefore, care should be taken while routing the feedback trace to avoid
coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or
parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between V
IN
and GND every cycle and is therefore a possible
source of noise. The SW node area should be minimized. In particular, the SW node should not be
inadvertently connected to a copper plane or pour.
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