Datasheet

I
PK+(CL)
=
R
CL
1.5A x (150 m: + R
CL
)
+ I
OR(MAX)
I
PK+
= I
O(max)
+
2
I
OR(max)
I
AVE
=
(R
CL
+ 0.11:x V
IN(max)
I
O(max)
x R
CL
x (V
IN(max)
- V
OUT
)
R
CL
=
1.0A x 0.11:
I
PK-
- 1.0A
I
PK-
= I
O(max)
-
2
I
OR(min)
LM5010
SNVS307F –SEPTEMBER 2004–REVISED FEBRUARY 2013 www.ti.com
INCREASING THE CURRENT LIMIT THRESHOLD
The current limit threshold is nominally 1.25A, with a minimum guaranteed value of 1.0A. If, at maximum load
current, the lower peak of the inductor current (I
PK-
in Figure 13) exceeds 1.0A, resistor R
CL
must be added
between S
GND
and I
SEN
to increase the current limit threshold to equal or exceed that lower peak current. This
resistor diverts some of the recirculating current from the internal sense resistor so that a higher current level is
needed to switch the internal current limit comparator. I
PK-
is calculated from:
(20)
where I
O(max)
is the maximum load current, and I
OR(min)
is the minimum ripple current calculated using
Equation 14. R
CL
is calculated from:
(21)
where 0.11Ω is the minimum value of the internal resistance from S
GND
to I
SEN
. The next smaller standard value
resistor should be used for R
CL
. With the addition of R
CL
it is necessary to check the average and peak current
values to ensure they do not exceed the LM5010 limits. At maximum load current the average current through
the internal sense resistor is:
(22)
If I
AVE
is less than 2.0A no changes are necessary. If it exceeds 2.0A, R
CL
must be reduced. The upper peak of
the inductor current (I
PK+
), at maximum load current, is calculated using the following:
(23)
where I
OR(max)
is calculated using Equation 11. If I
PK+
exceeds 3.5A , the inductor value must be increased to
reduce the ripple amplitude. This will necessitate recalculation of I
OR(min)
, I
PK-
, and R
CL
.
When the circuit is in current limit, the upper peak current out of the SW pin is
(24)
The inductor L1 and diode D1 must be rated for this current.
PC BOARD LAYOUT
The LM5010 regulation, over-voltage, and current limit comparators are very fast, and will respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible, and all the components must be as close as possible to their associated pins.
The current loop formed by D1, L1, C2, and the S
GND
and I
SEN
pins should be as small as possible. The ground
connection from C2 to C1 should be as short and direct as possible. If it is expected that the internal dissipation
of the LM5010 will produce high junction temperatures during normal operation, good use of the PC board’s
ground plane can help considerably to dissipate heat. The exposed pad on the IC package bottom can be
soldered to a ground plane, and that plane should both extend from beneath the IC, and be connected to
exposed ground plane on the board’s other side using as many vias as possible. The exposed pad is internally
connected to the IC substrate.
The use of wide PC board traces at the pins, where possible, can help conduct heat away from the IC. The four
No Connect pins on the HTSSOP package are not electrically connected to any part of the IC, and may be
connected to ground plane to help dissipate heat from the package. Judicious positioning of the PC board within
the end product, along with the use of any available air flow (forced or natural convection) can help reduce the
junction temperature.
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