Datasheet
Cff
3 x t
ON (max)
(R3//R4)
t
R1
280k
0.1 PF
C5
LM5008A
C4
D1
L1
220 PH
V
OUT
GND
VIN
RT/SD
RCL
VCC
BST
SW
FB
RTN
V
IN
GND
SHUTDOWN
(TP1SD)
R6
8V to 75V
Input
0:
1 PF
C1
R2
715k
0.1 PF
C3
0.47 PF
R3
3.01k
R4
3.01k
R5
0.39:
C2
22 PF
5V
Cff
0.01 PF
R1
280k
0.1 PF
C5
LM5008A
C4
D1
L1
220 PH
V
OUT
GND
VIN
RT/SD
RCL
VCC
BST
SW
FB
RTN
V
IN
GND
SHUTDOWN
(TP1SD)
R6
8V to 75V
Input
0:
1 PF
C1
R2
715k
0.1 PF
C3
0.47 PF
R3
3.01k
R4
3.01k
R5
0.82:
C2
22 PF
5V
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Output Ripple Control
Figure 2. Lowest Cost Configuration
Option B) Intermediate Ripple Configuration: This configuration generates less ripple at V
OUT
than
option A above by the addition of one capacitor (Cff) across R3, as shown in Figure 3.
Figure 3. Intermediate Ripple Configuration
Since the output ripple is passed by Cff to the FB pin with little or no attenuation, R5 can be reduced so
the minimum ripple at V
OUT
is ≊25 mVp-p. The minimum value for Cff is calculated from:
(2)
where t
ON(max)
is the maximum on-time (at minimum V
IN
), and R3//R4 is the parallel equivalent of the
feedback resistors. The ripple at V
OUT
ranges from 26 mVp-p to 64 mVp-p over the input voltage range.
See Figure 8.
Option C) Minimum Ripple Configuration: To obtain minimum ripple at V
OUT
, R5 is set to 0Ω, and RA,
CA, and CB are added to generate the required ripple for the FB pin. In this configuration, the output ripple
is determined primarily by the characteristics of the output capacitance and the inductor’s ripple current.
See Figure 4.
3
SNVA380C–March 2009–Revised April 2013 AN-1925 LM5008A Evaluation Board
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