Datasheet

LM5005
www.ti.com SNVS397D –SEPTEMBER 2005–REVISED MARCH 2013
PIN DESCRIPTIONS
Pin(S) Name Description Application Information
Vcc tracks Vin up to 9V, beyond 9V Vcc is regulated to 7 Volts.
A 0.1uF to 1uF ceramic decoupling capacitor is required. An
1 VCC Output of the bias regulator
external voltage (7.5V – 14V) can be applied to this pin to
reduce internal power dissipation.
If the SD pin voltage is below 0.7V the regulator will be in a low
power state. If the SD pin voltage is between 0.7V and 1.225V
the regulator will be in standby mode. If the SD pin voltage is
2 SD Shutdown or UVLO input above 1.225V the regulator will be operational. An external
voltage divider can be used to set a line undervoltage shutdown
threshold. If the SD pin is left open circuit, a 5µA pull-up current
source configures the regulator fully operational.
3, 4 Vin Input supply voltage Nominal operating range: 7V to 75V
The internal oscillator can be synchronized to an external clock
5 SYNC Oscillator synchronization input or output with an external pull-down device. Multiple LM5005 devices can
be synchronized together by connection of their SYNC pins.
The loop compensation network should be connected between
6 COMP Output of the internal error amplifier
this pin and the FB pin.
This pin is connected to the inverting input of the internal error
7 FB Feedback signal from the regulated output
amplifier. The regulation threshold is 1.225V.
The internal oscillator is set with a single resistor, connected
8 RT Internal oscillator frequency set input between this pin and the AGND pin. The recommended
frequency range is 50KHz to 500KHz.
An external capacitor connected between this pin and the AGND
9 RAMP Ramp control signal pin sets the ramp slope used for current mode control.
Recommended capacitor range 50pF to 2000pF.
10 AGND Analog ground Internal reference for the regulator control functions
An external capacitor and an internal 10µA current source set
the time constant for the rise of the error amp reference. The SS
11 SS Soft-start
pin is held low during standby, Vcc UVLO and thermal
shutdown.
12 OUT Output voltage connection Connect directly to the regulated output voltage.
13, 14 PGND Power ground Low side reference for the PRE switch and the IS sense resistor.
Current measurement connection for the re-circulating diode. An
internal sense resistor and a sample/hold circuit sense the diode
15, 16 IS Current sense current near the conclusion of the off-time. This current
measurement provides the DC level of the emulated current
ramp.
The source terminal of the internal buck switch. The SW pin
17, 18 SW Switching node should be connected to the external Schottky diode and to the
buck inductor.
This open drain output can be connected to SW pin to aid
charging the bootstrap capacitor during very light load conditions
Pre-charge assist for the bootstrap or in applications where the output may be pre-charged before
19 PRE
capacitor the LM5005 is enabled. An internal pre-charge MOSFET is
turned on for 250nS each cycle just prior to the on-time interval
of the buck switch.
An external capacitor is required between the BST and the SW
pins. A 0.022µF ceramic capacitor is recommended. The
20 BST Boost input for bootstrap capacitor
capacitor is charged from Vcc via an internal diode during the
off-time of the buck switch.
NA EP Exposed Pad Exposed metal pad on the underside of the device. It is
recommended to connect this pad to the PWB ground plane, in
order to aid in heat dissipation.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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