Datasheet
PWM
FB
5k
COMP
5V
VOUT
LM5001
1
1
¸
¸
¹
·
¨
¨
©
§
1
C
1
C
2
R
2
R
FEEDBACK
R
1
1.3V
1.26V
F
DC_POLE
=
F
POLE
=
F
ZERO
=
2S x R
1
x(C
1
+ C
2
)
C
1
xC
2
2S x R
2
xC
2
2S x R
2
x
C
1
+ C
2
LM5001
,
LM5001-Q1
SNVS484G –JANUARY 2007–REVISED APRIL 2014
www.ti.com
Feature Description (continued)
An external set-point resistor divider from VIN to GND can be used to determine the minimum operating input
range of the regulator. The divider must be designed such that the EN pin exceeds the 1.26 V standby threshold
when VIN is in the desired operating range. The internal 6 µA current source should be included when
determining the resistor values. The shutdown and standby thresholds have 100 mV hysteresis to prevent noise
from toggling between modes. When the VIN voltage is below 3.5 VDC during start-up and the operating
temperature is below –20°C, the EN pin should have a pull-up resistor provides 2 µA or greater current. The EN
pin is internally protected by a 6 V Zener diode through a 1 kΩ resistor. The enabling voltage may exceed the
Zener voltage, however the Zener current should be limited to less than 4 mA.
7.3.5 Error Amplifier and PWM Comparator
An internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference. The output of the error amplifier is connected to the
COMP pin allowing the user to add loop compensation, typically a Type II network, as illustrated in Figure 13.
This network creates a low frequency pole that rolls off the high DC gain of the amplifier, which is necessary to
accurately regulate the output voltage. F
DC_POLE
is the closed loop unity gain (0 dB) frequency of this pole. A zero
provides phase boost near the closed loop unity gain frequency, and a high frequency pole attenuates switching
noise. The PWM comparator compares the current sense signal from the current sense amplifier to the error
amplifier output voltage at the COMP pin.
Figure 13. Type II Compensator
When isolation between primary and secondary circuits is required, the Error Amplifier is usually disabled by
connecting the FB pin to GND. This allows the COMP pin to be driven directly by the collector of an opto-coupler.
In isolated designs the external error amplifier is located on the secondary circuit and drives the opto-coupler
LED. The compensation network is connected to the secondary side error amplifier. An example of an isolated
regulator with an opto-coupler is shown in Figure 19.
7.3.6 Current Amplifier and Slope Compensation
The LM5001 employs peak current mode control which also provides a cycle-by-cycle over current protection
feature. An internal 50 mΩ current sense resistor measures the current in the power MOSFET source. The sense
resistor voltage is amplified 30 times to provide a 1.5 V/A signal into the current limit comparator. Current limiting
is initiated if the internal current limit comparator input exceeds the 1.5 V threshold, corresponding to 1 A. When
the current limit comparator is triggered, the SW output pin immediately switches to a high impedance state.
10 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: LM5001 LM5001-Q1