Datasheet

m1
#
V
IN
R
DSON
L
(in V/s)
n = 1+
2mc
m1
(no unit)
Leff =
L
(D')
2
Zc
(in rad/s)
2fs
nD'
#
A
DC(DB)
= 20log
10
{[(ZcLeff)// R
L
]//R
L
}
(in dB)
R
FB1
+ R
FB2
R
FB2
(
)
g
m
R
O
D'
R
DSON
f
PC2
=
1
2SC
C2
(R
C
//R
O
)
(in Hz)
LM5000
SNVS176D –MAY 2004–REVISED MARCH 2007 www.ti.com
Now R
C
can be chosen with the selected value for C
C
. Check to make sure that the pole f
PC
is still in the 10Hz to
100Hz range, change each value slightly if needed to ensure both component values are in the recommended
range. After checking the design at the end of this section, these values can be changed a little more to optimize
performance if desired. This is best done in the lab on a bench, checking the load step response with different
values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should
produce a stable, high performance circuit. For improved transient response, higher values of R
C
(within the
range of values) should be chosen. This will improve the overall bandwidth which makes the regulator respond
more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more
in depth discussion of compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, C
C2
, directly from the compensation pin V
C
to ground, in parallel with the series combination of
R
C
and C
C
. The pole should be placed at the same frequency as f
Z1
, the ESR zero. The equation for this pole
follows:
(13)
To ensure this equation is valid, and that C
C2
can be used without negatively impacting the effects of R
C
and C
C
,
f
PC2
must be greater than 10f
PC
.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP
zero. This is done by calculating the open-loop DC gain, A
DC
. After this value is known, you can calculate the
crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The
point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is
at less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also
be improved some by adding C
C2
as discussed earlier in the section. The equation for A
DC
is given below with
additional equations required for the calculation:
(14)
(15)
(16)
(17)
mc ≊ 0.072fs (in A/s) (18)
where
• R
L
is the minimum load resistance
• V
IN
is the maximum input voltage
• R
DSON
is the value chosen from the graph "R
DSON
vs. V
IN
" in the Typical Performance Characteristics
section (19)
SWITCH VOLTAGE LIMITS
In a flyback regulator, the maximum steady-state voltage appearing at the switch, when it is off, is set by the
transformer turns ratio, N, the output voltage, V
OUT
, and the maximum input voltage, V
IN
(Max):
V
SW(OFF)
= V
IN
(Max) + (V
OUT
+V
F
)/N
where
• V
F
is the forward biased voltage of the output diode, and is typically 0.5V for Schottky diodes and 0.8V for
ultra-fast recovery diodes (20)
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