Datasheet

LM4950
www.ti.com SNAS174E –JULY 2003–REVISED MAY 2013
The Output Power vs. Power Supply Voltage graph in Typical Performance Characteristics for an 8Ω load
indicates a minimum supply voltage of 10.2V. The commonly used 12V supply voltage easily meets this. The
additional voltage creates the benefit of headroom, allowing the LM4950 to produce peak output power in excess
of 4W without clipping or other audible distortion. The choice of supply voltage must also not create a situation
that violates of maximum power dissipation as explained in the POWER DISSIPATION section. After satisfying
the LM4950's power dissipation requirements, the minimum differential gain needed to achieve 4W dissipation in
an 8Ω BTL load is found using Equation 10.
(10)
Thus, a minimum gain of 18.9 allows the LM4950's to reach full output swing and maintain low noise and THD+N
performance. For this example, let A
V-BTL
= 19. The amplifier's overall BTL gain is set using the input (RIN
A
) and
feedback (R) resistors of the first amplifier in the series BTL configuration. Additionaly, A
V-BTL
is twice the gain set
by the first amplifier's R
IN
and R
f
. With the desired input impedance set at 20kΩ, the feedback resistor is found
using Equation 11.
R
f
/ R
IN
= A
V-BTL
/ 2 (11)
The value of R
f
is 190kΩ (choose 191kΩ, the closest value). The nominal output power is 4W.
The last step in this design example is setting the amplifier's -3dB frequency bandwidth. To achieve the desired
±0.25dB pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the
lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth
limit. The gain variation for both response limits is 0.17dB, well within the ±0.25dB-desired limit. The results are
an
f
L
= 50Hz / 5 = 10Hz (12)
and an
f
L
= 20kHz x 5 = 100kHz (13)
As mentioned in SELECTING EXTERNAL COMPONENTS, R
INA
and C
INA
create a highpass filter that sets the
amplifier's lower bandpass frequency limit. Find the coupling capacitor's value using Equation 14.
C
i
= 1 / 2πR
IN
f
L
(14)
The result is
1 / (2πx20kΩx10Hz) = 0.795µF (15)
Use a 0.82µF capacitor, the closest standard value.
The product of the desired high frequency cutoff (100kHz in this example) and the differential gain A
VD
,
determines the upper passband response limit. With A
VD
= 7 and f
H
= 100kHz, the closed-loop gain bandwidth
product (GBWP) is 700kHz. This is less than the LM4950's 3.5MHz GBWP. With this margin, the amplifier can
be used in designs that require more differential gain while avoiding performance restricting bandwidth
limitations.
RECOMMENDED PRINTED CIRCUIT BOARD LAYOUT
Figure 67 through Figure 69 show the recommended two-layer PC board layout that is optimized for the DDPAK-
packaged, SE-configured LM4950 and associated external components. Figure 70 through Figure 72 show the
recommended two-layer PC board layout that is optimized for the DDPAK-packaged, BTL-configured LM4950
and associated external components. These circuits are designed for use with an external 12V supply and
4Ω(min)(SE) or 8Ω(min)(BTL) speakers.
These circuit boards are easy to use. Apply 12V and ground to the board's V
DD
and GND pads, respectively.
Connect a speaker between the board's OUT
A
and OUT
B
outputs.
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