Datasheet

LM49450
www.ti.com SNAS440D –FEBRUARY 2008–REVISED MAY 2013
Timing Characteristics
(1)(2)
(continued)
The following specifications apply for Headphone: A
V
= 0dB, R
L(LS)
= 8Ω, R
L(HP)
= 32Ω, f = 1kHz, unless otherwise specified.
Limits apply for T
A
= 25°C.
LM49450
Units
Symbol Parameter Conditions
(Limits)
Typical
(3)
Limit
(4)
DATA Hold Time from BCLK 10 ns (min)
t
DHT
Rising Edge
CONTROL INTERFACE TIMING
SCLK Frequency 400 kHz (max)
Hold Time (repeated START 0.6 μs (min)
1
Condition)
2 Clock Low Time 1.3 μs (min)
3 Clock High Time 600 ns (min)
Setup Time for a Repeated 600 ns (min)
4
START Condition
Data Hold Time Output 300 ns (min)
5
0 ns (min)
Input
900 ns (max)
6 Data Setup Time 100 ns (min)
20+0.1C
B
ns (min)
7 Rise Time of SDA and SCL
300 ns (max)
Fall Time of SDA and SCL 15+0.1C
B
ns (min)
8
300 ns (max)
9 Setup Time for STOP Condition 600 ns (min)
Bus Free time Between a STOP 1.3 μs ( min)
10
and START Condition
Bus Capacitance 10 pF (min)
C
B
200 pF (max)
PIN DESCRIPTIONS
Pin Name Description
1 C1P Charge Pump Flying Capacitor Positive Terminal
2 CPGND Charge Pump Ground
3 SDA I
2
C Serial Data Input
4 DGND Digital Ground
5 I
2
S_WS I
2
S Word Select Input
6 I
2
S_SDI I
2
S Serial Data Input
7 I
2
S_CLK I
2
S Clock Input
8 MCLK Master Clock
9 SCL I
2
C Clock Input
10 DV
DD
Digital Core Power Supply
11 IOV
DD
Digital Interface Power Supply
12 GND Analog Ground
13 REF DAC Reference Bypass
14 INR Right Channel Analog Input
15 INL Left Channel Analog Input
16 V
DD
Analog Power Supply
17 BYPASS Mid-Rail Bias Bypass
18, 24 LSV
DD
Speaker Power Supply
19 LLS+ Left Channel Non-Inverting Speaker Output
20 LLS- Left Channel Inverting Speaker Output
21 LSGND Speaker Ground
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