Datasheet

LM49450
www.ti.com SNAS440D –FEBRUARY 2008–REVISED MAY 2013
f = 1 / 2πR
IN
C
IN
where
• the value of R
IN
is typically 20kΩ (1)
The input capacitors can also be used to remove low frequency content from the audio signal. Small speakers
cannot reproduce, and may even be damaged by low frequencies. High pass filtering the audio signal helps
protect the speakers. When the LM49450 is using a single-ended source, power supply noise on the ground is
seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a
GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors
with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR.
PCB Layout Guidelines
Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due
to trace resistance between the LM49450 and the load results in decreased output power and efficiency. Trace
resistance between the power supply and ground has the same effect as a poorly regulated supply, increased
ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize
losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio
performance, minimizes crosstalk between channels and prevents switching noise from interfering with the audio
signal. Use of power and ground planes is recommended.
Place all digital components and route digital signal traces as far as possible from analog components and
traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines
must cross either over or under each other, ensure that they cross in a perpendicular fashion.
Exposed DAP Mounting Considerations
The LM49450 WQFN package features an exposed die-attach (thermal) pad on its backside. The exposed pad
provides a direct heat conduction path from the die to the PCB, reducing the thermal resistance of the package.
Connect the exposed pad to GND with a large pad and via to a large GND plane on the bottom of the PCB for
best heat distribution.
Revision Table
Rev Date Description
1.0 12/18/07 Initial release.
1.01 09/26/08 Corrected the package drawing.
On Table 5 (Common DAC Clock..., col DAC MODE = 2b01... sample 8...), changed
1.02 08/04/11
2.084 to 2.048.
D 05/03/13 Changed layout of National Data Sheet to TI format.
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