Datasheet

LM49450
SNAS440D –FEBRUARY 2008–REVISED MAY 2013 www.ti.com
I
2
S CLOCK REGISTER (0x04h)
Default value is 0x00h.
Table 13. I
2
S Clock Register
Bit Name Value Description
Sets divider ratio to derive the I
2
S clock from the divided MCLK in I
2
S
master mode
B7 B6 B5 B4
DIVIDE BY RATIO
0 0 0 0 1 —
0 0 0 1 2 —
0 0 1 0 4 —
0 1 1 1 6 —
I2S_CLK_3
0 0 0 0 8 —
(B7)
0 0 1 1 10 —
I2S_CLK_2
(B6)
0 1 0 0 16 —
B7:B4
I2S_CLK_1
0 1 1 1 20 —
(B5)
I2S_CLK_0
1 0 0 0 2.5 2.5
(B4)
1 0 0 1 3 1:3
1 0 1 0 3.90625 32:125
1 0 1 1 5 1:5
1 1 0 0 7.8125 16:125
1 1 0 1 — —
1 1 1 0 — —
1 1 1 1 — —
B3 B2 Determines the bit length per data word of I
2
S_WS in I
2
S master mode
I2S_WS_1
0 0 16
(B3)
B3:B2 0 1 25
I2S_WS_0(
1 0 32
B2)
1 1 —
I
2
S WS slave mode. The LM49450 drives the I
2
S WS signal from the
0
I2S_WS line.
I2S_WS_M
B1
S
I
2
S WS master mode. The LM49450 generates the I2S WS signal.
1
I2S_WS line is driven by the LM49450
I
2
S clock slave mode. The LM49450 derives its I
2
S clock from the
0
I2S_CLK line.
I2S_CLK_M
B0
S
I
2
S clock master mode. The LM49450 generates the I
2
S clock signal.
1
I2S_CLK line is driven by the LM49450.
HEADPHONE 3D CONFIGURATION REGISTER (0x05h)
Default value is 0x00h.
Table 14. Headphone 3D Configuration Register
Bit Name Value Description
B7 RESERVED X UNUSED
0 No Attenuation
B6 HP_3DATTN
1 Output signals are attenuated by 6dB
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